derek.holloway
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98 lines
6.0 KiB
LLVM
98 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O2 -mtriple riscv64 -mattr=+v,+m,+zbb -enable-subreg-liveness \
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; RUN: -verify-machineinstrs < %s \
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; RUN: | FileCheck %s
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@var_47 = dso_local global [2 x i16] [i16 -32732, i16 19439], align 2
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@__const._Z3foov.var_49 = private unnamed_addr constant [2 x i16] [i16 157, i16 24062], align 2
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@__const._Z3foov.var_48 = private unnamed_addr constant [2 x i8] c"\AEN", align 1
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@__const._Z3foov.var_46 = private unnamed_addr constant [2 x i16] [i16 729, i16 -32215], align 2
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@__const._Z3foov.var_45 = private unnamed_addr constant [2 x i16] [i16 -27462, i16 -1435], align 2
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@__const._Z3foov.var_44 = private unnamed_addr constant [2 x i16] [i16 22611, i16 -18435], align 2
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@__const._Z3foov.var_40 = private unnamed_addr constant [2 x i16] [i16 -19932, i16 -26252], align 2
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define void @_Z3foov() {
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; CHECK-LABEL: _Z3foov:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a1, a0, 3
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; CHECK-NEXT: add a0, a1, a0
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; CHECK-NEXT: sub sp, sp, a0
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
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; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_49)
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; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_49)
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; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_48)
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; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_48)
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; CHECK-NEXT: vle8.v v10, (a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
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; CHECK-NEXT: vs1r.v v10, (a0) # vscale x 8-byte Folded Spill
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; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_46)
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; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_46)
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; CHECK-NEXT: vle16.v v10, (a0)
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; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_45)
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; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_45)
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; CHECK-NEXT: vle16.v v12, (a0)
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
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; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_40)
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; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_40)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: lui a0, 1048572
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; CHECK-NEXT: addi a0, a0, 928
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; CHECK-NEXT: vmsbc.vx v0, v8, a0
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
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; CHECK-NEXT: vl1r.v v14, (a0) # vscale x 8-byte Folded Reload
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, tu, mu
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; CHECK-NEXT: vsext.vf2 v8, v14, v0.t
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; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_44)
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; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_44)
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vle16.v v14, (a0)
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; CHECK-NEXT: lui a0, %hi(var_47)
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; CHECK-NEXT: addi a0, a0, %lo(var_47)
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; CHECK-NEXT: vsseg4e16.v v8, (a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a1, a0, 3
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; CHECK-NEXT: add a0, a1, a0
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> poison, ptr nonnull @__const._Z3foov.var_49, i64 2)
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%1 = tail call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.i64(<vscale x 8 x i8> poison, ptr nonnull @__const._Z3foov.var_48, i64 2)
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%2 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> poison, ptr nonnull @__const._Z3foov.var_46, i64 2)
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%3 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> poison, ptr nonnull @__const._Z3foov.var_45, i64 2)
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tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() #2
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%4 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> poison, ptr nonnull @__const._Z3foov.var_44, i64 2)
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%5 = tail call i64 @llvm.riscv.vsetvli.i64(i64 2, i64 1, i64 1)
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%6 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> poison, ptr nonnull @__const._Z3foov.var_40, i64 2)
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%7 = tail call i64 @llvm.riscv.vsetvli.i64(i64 2, i64 1, i64 1)
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%8 = tail call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i16.i16.i64(<vscale x 8 x i16> %6, i16 -15456, i64 2)
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%9 = tail call i64 @llvm.riscv.vsetvli.i64(i64 2, i64 1, i64 1)
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%10 = tail call <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %8, i64 2, i64 0)
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%v_0 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, <vscale x 8 x i16> %10, i32 0)
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%v_1 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_0, <vscale x 8 x i16> %2, i32 1)
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%v_2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_1, <vscale x 8 x i16> %3, i32 2)
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%v_3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_2, <vscale x 8 x i16> %4, i32 3)
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tail call void @llvm.riscv.vsseg4.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_3, ptr nonnull @var_47, i64 2, i64 4)
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ret void
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}
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