derek.holloway
7502bf64a4
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255 lines
8.4 KiB
LLVM
255 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfh -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfh -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV64IZFH %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV32IZHINX %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV64IZHINX %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV32IZFHMIN %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV64IZFHMIN %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin -verify-machineinstrs \
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; RUN: < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV32IZHINXMIN %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin -verify-machineinstrs \
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; RUN: < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV64IZHINXMIN %s
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; This file tests cases where simple floating point operations can be
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; profitably handled though bit manipulation if a soft-float ABI is being used
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; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
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; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
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; in cases where we perform custom legalisation (e.g. RV64F).
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define half @fneg(half %a) nounwind {
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; RV32I-LABEL: fneg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1048568
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IZFH-LABEL: fneg:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: lui a1, 1048568
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; RV32IZFH-NEXT: xor a0, a0, a1
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; RV32IZFH-NEXT: ret
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;
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; RV64I-LABEL: fneg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 1048568
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IZFH-LABEL: fneg:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: lui a1, 1048568
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; RV64IZFH-NEXT: xor a0, a0, a1
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; RV64IZFH-NEXT: ret
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;
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; RV32IZHINX-LABEL: fneg:
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; RV32IZHINX: # %bb.0:
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; RV32IZHINX-NEXT: fneg.h a0, a0
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; RV32IZHINX-NEXT: ret
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;
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; RV64IZHINX-LABEL: fneg:
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; RV64IZHINX: # %bb.0:
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; RV64IZHINX-NEXT: fneg.h a0, a0
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; RV64IZHINX-NEXT: ret
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;
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; RV32IZFHMIN-LABEL: fneg:
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; RV32IZFHMIN: # %bb.0:
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; RV32IZFHMIN-NEXT: lui a1, 1048568
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; RV32IZFHMIN-NEXT: xor a0, a0, a1
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; RV32IZFHMIN-NEXT: ret
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;
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; RV64IZFHMIN-LABEL: fneg:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: lui a1, 1048568
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; RV64IZFHMIN-NEXT: xor a0, a0, a1
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; RV64IZFHMIN-NEXT: ret
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;
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; RVIZHINXMIN-LABEL: fneg:
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; RVIZHINXMIN: # %bb.0:
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; RVIZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h def $x10
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; RVIZHINXMIN-NEXT: lui a1, 1048568
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; RVIZHINXMIN-NEXT: xor a0, a0, a1
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; RVIZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
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; RVIZHINXMIN-NEXT: ret
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%1 = fneg half %a
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ret half %1
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}
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define half @fabs(half %a) nounwind {
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; RV32I-LABEL: fabs:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 17
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; RV32I-NEXT: srli a0, a0, 17
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; RV32I-NEXT: ret
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;
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; RV32IZFH-LABEL: fabs:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: slli a0, a0, 17
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; RV32IZFH-NEXT: srli a0, a0, 17
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; RV32IZFH-NEXT: ret
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;
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; RV64I-LABEL: fabs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 49
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; RV64I-NEXT: srli a0, a0, 49
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; RV64I-NEXT: ret
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;
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; RV64IZFH-LABEL: fabs:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: slli a0, a0, 49
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; RV64IZFH-NEXT: srli a0, a0, 49
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; RV64IZFH-NEXT: ret
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;
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; RV32IZHINX-LABEL: fabs:
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; RV32IZHINX: # %bb.0:
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; RV32IZHINX-NEXT: fabs.h a0, a0
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; RV32IZHINX-NEXT: ret
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;
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; RV64IZHINX-LABEL: fabs:
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; RV64IZHINX: # %bb.0:
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; RV64IZHINX-NEXT: fabs.h a0, a0
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; RV64IZHINX-NEXT: ret
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;
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; RV32IZFHMIN-LABEL: fabs:
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; RV32IZFHMIN: # %bb.0:
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; RV32IZFHMIN-NEXT: slli a0, a0, 17
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; RV32IZFHMIN-NEXT: srli a0, a0, 17
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; RV32IZFHMIN-NEXT: ret
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;
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; RV64IZFHMIN-LABEL: fabs:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: slli a0, a0, 49
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; RV64IZFHMIN-NEXT: srli a0, a0, 49
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; RV64IZFHMIN-NEXT: ret
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;
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; RV32IZHINXMIN-LABEL: fabs:
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; RV32IZHINXMIN: # %bb.0:
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; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h def $x10
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; RV32IZHINXMIN-NEXT: slli a0, a0, 17
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; RV32IZHINXMIN-NEXT: srli a0, a0, 17
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; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
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; RV32IZHINXMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: fabs:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h def $x10
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; RV64IZHINXMIN-NEXT: slli a0, a0, 49
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; RV64IZHINXMIN-NEXT: srli a0, a0, 49
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; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
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; RV64IZHINXMIN-NEXT: ret
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%1 = call half @llvm.fabs.f16(half %a)
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ret half %1
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}
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; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
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; operations if half precision floating point isn't supported. A combine could
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; be written to do the same even when f16 is legal.
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define half @fcopysign_fneg(half %a, half %b) nounwind {
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; RV32I-LABEL: fcopysign_fneg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: lui a2, 1048568
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; RV32I-NEXT: slli a0, a0, 17
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; RV32I-NEXT: and a1, a1, a2
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; RV32I-NEXT: srli a0, a0, 17
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IZFH-LABEL: fcopysign_fneg:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x fa5, a1
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; RV32IZFH-NEXT: fmv.h.x fa4, a0
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; RV32IZFH-NEXT: fsgnjn.h fa5, fa4, fa5
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; RV32IZFH-NEXT: fmv.x.h a0, fa5
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; RV32IZFH-NEXT: ret
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;
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; RV64I-LABEL: fcopysign_fneg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: not a1, a1
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; RV64I-NEXT: lui a2, 1048568
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; RV64I-NEXT: slli a0, a0, 49
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: srli a0, a0, 49
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IZFH-LABEL: fcopysign_fneg:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x fa5, a1
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; RV64IZFH-NEXT: fmv.h.x fa4, a0
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; RV64IZFH-NEXT: fsgnjn.h fa5, fa4, fa5
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; RV64IZFH-NEXT: fmv.x.h a0, fa5
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; RV64IZFH-NEXT: ret
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;
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; RV32IZHINX-LABEL: fcopysign_fneg:
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; RV32IZHINX: # %bb.0:
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; RV32IZHINX-NEXT: fsgnjn.h a0, a0, a1
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; RV32IZHINX-NEXT: ret
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;
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; RV64IZHINX-LABEL: fcopysign_fneg:
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; RV64IZHINX: # %bb.0:
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; RV64IZHINX-NEXT: fsgnjn.h a0, a0, a1
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; RV64IZHINX-NEXT: ret
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;
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; RV32IZFHMIN-LABEL: fcopysign_fneg:
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; RV32IZFHMIN: # %bb.0:
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; RV32IZFHMIN-NEXT: not a1, a1
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; RV32IZFHMIN-NEXT: lui a2, 1048568
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; RV32IZFHMIN-NEXT: slli a0, a0, 17
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; RV32IZFHMIN-NEXT: and a1, a1, a2
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; RV32IZFHMIN-NEXT: srli a0, a0, 17
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; RV32IZFHMIN-NEXT: or a0, a0, a1
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; RV32IZFHMIN-NEXT: ret
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;
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; RV64IZFHMIN-LABEL: fcopysign_fneg:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: not a1, a1
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; RV64IZFHMIN-NEXT: lui a2, 1048568
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; RV64IZFHMIN-NEXT: slli a0, a0, 49
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; RV64IZFHMIN-NEXT: and a1, a1, a2
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; RV64IZFHMIN-NEXT: srli a0, a0, 49
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; RV64IZFHMIN-NEXT: or a0, a0, a1
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; RV64IZFHMIN-NEXT: ret
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;
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; RV32IZHINXMIN-LABEL: fcopysign_fneg:
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; RV32IZHINXMIN: # %bb.0:
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; RV32IZHINXMIN-NEXT: # kill: def $x11_h killed $x11_h def $x11
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; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h def $x10
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; RV32IZHINXMIN-NEXT: not a1, a1
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; RV32IZHINXMIN-NEXT: lui a2, 1048568
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; RV32IZHINXMIN-NEXT: slli a0, a0, 17
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; RV32IZHINXMIN-NEXT: and a1, a1, a2
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; RV32IZHINXMIN-NEXT: srli a0, a0, 17
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; RV32IZHINXMIN-NEXT: or a0, a0, a1
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; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
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; RV32IZHINXMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: fcopysign_fneg:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: # kill: def $x11_h killed $x11_h def $x11
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; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h def $x10
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; RV64IZHINXMIN-NEXT: not a1, a1
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; RV64IZHINXMIN-NEXT: lui a2, 1048568
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; RV64IZHINXMIN-NEXT: slli a0, a0, 49
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; RV64IZHINXMIN-NEXT: and a1, a1, a2
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; RV64IZHINXMIN-NEXT: srli a0, a0, 49
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; RV64IZHINXMIN-NEXT: or a0, a0, a1
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; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
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; RV64IZHINXMIN-NEXT: ret
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%1 = fneg half %b
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%2 = call half @llvm.copysign.f16(half %a, half %1)
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ret half %2
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}
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