derek.holloway
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75 lines
2.1 KiB
LLVM
75 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; For each of these examples, it is fewer instructions to narrow the load and
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; then shift (which is an opportunity that can be exposed by doing the mask
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; before the shift).
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define ptr @narrow_to_lbu(ptr %a, ptr %b) {
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; RV32I-LABEL: narrow_to_lbu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lbu a0, 0(a0)
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; RV32I-NEXT: slli a0, a0, 4
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: narrow_to_lbu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lbu a0, 0(a0)
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; RV64I-NEXT: slli a0, a0, 4
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: ret
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%1 = load i16, ptr %a, align 2
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%2 = shl i16 %1, 1
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%3 = and i16 %2, 510
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%4 = zext nneg i16 %3 to i64
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%5 = getelementptr inbounds double, ptr %b, i64 %4
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ret ptr %5
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}
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define ptr @narrow_to_lhu(ptr %a, ptr %b) {
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; RV32I-LABEL: narrow_to_lhu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lhu a0, 0(a0)
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; RV32I-NEXT: slli a0, a0, 4
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: narrow_to_lhu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lhu a0, 0(a0)
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; RV64I-NEXT: slli a0, a0, 4
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: ret
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%1 = load i32, ptr %a, align 4
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%2 = shl i32 %1, 1
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%3 = and i32 %2, 131070
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%4 = zext nneg i32 %3 to i64
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%5 = getelementptr inbounds double, ptr %b, i64 %4
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ret ptr %5
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}
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define ptr @narrow_to_lwu(ptr %a, ptr %b) {
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; RV32I-LABEL: narrow_to_lwu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: slli a0, a0, 4
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: narrow_to_lwu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lwu a0, 0(a0)
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; RV64I-NEXT: slli a0, a0, 4
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: ret
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%1 = load i64, ptr %a, align 8
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%2 = shl i64 %1, 1
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%3 = and i64 %2, 8589934590
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%4 = getelementptr inbounds double, ptr %b, i64 %3
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ret ptr %4
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}
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