derek.holloway
7502bf64a4
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258 lines
9.3 KiB
YAML
258 lines
9.3 KiB
YAML
# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s
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# Combined tests for outlining with CFI instructions on RISC-V:
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# 1) All CFIs present in candidate: outline as tail-call and keep CFIs.
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# 2) Partial CFIs in function (extra outside candidate): do not outline.
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# 3) CFIs present but candidate is not a tail-call: do not outline.
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--- |
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define void @funcA(i32 %a, i32 %b) nounwind { ret void }
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define void @funcB(i32 %a, i32 %b) nounwind { ret void }
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define void @funcC(i32 %a, i32 %b) nounwind { ret void }
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define void @funcD(i32 %a, i32 %b) nounwind { ret void }
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define void @funcE(i32 %a, i32 %b) nounwind { ret void }
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define void @funcF(i32 %a, i32 %b) nounwind { ret void }
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...
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# Case 1: All CFIs present; expect outlining and CFIs retained in outlined body.
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---
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name: funcA
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: funcA
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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;
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; RV64I-MO-LABEL: name: funcA
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -4
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -8
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: funcB
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: funcB
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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;
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; RV64I-MO-LABEL: name: funcB
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -4
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -8
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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# Case 2: Partial CFIs (extra CFI outside candidate in funcD); expect no outlining.
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---
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name: funcC
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: funcC
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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;
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; RV64I-MO-LABEL: name: funcC
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -4
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -8
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: funcD
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: funcD
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -16
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0
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; RV32I-MO-NEXT: $x11 = ORI $x11, 1023
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4
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; RV32I-MO-NEXT: $x12 = ADDI $x10, 17
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8
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; RV32I-MO-NEXT: $x11 = AND $x12, $x11
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12
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; RV32I-MO-NEXT: $x10 = SUB $x10, $x11
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; RV32I-MO-NEXT: PseudoRET
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;
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; RV64I-MO-LABEL: name: funcD
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -16
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0
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; RV64I-MO-NEXT: $x11 = ORI $x11, 1023
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4
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; RV64I-MO-NEXT: $x12 = ADDI $x10, 17
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8
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; RV64I-MO-NEXT: $x11 = AND $x12, $x11
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12
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; RV64I-MO-NEXT: $x10 = SUB $x10, $x11
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; RV64I-MO-NEXT: PseudoRET
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CFI_INSTRUCTION offset $x1, -16
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -4
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -8
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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# Case 3: CFIs present but candidate is not a tail-call; expect no outlining.
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---
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name: funcE
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: funcE
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0
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; RV32I-MO-NEXT: $x11 = ORI $x11, 1023
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4
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; RV32I-MO-NEXT: $x12 = ADDI $x10, 17
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8
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; RV32I-MO-NEXT: $x11 = AND $x12, $x11
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12
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; RV32I-MO-NEXT: $x10 = SUB $x10, $x11
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; RV32I-MO-NEXT: $x10 = ADDI $x10, 1
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; RV32I-MO-NEXT: PseudoRET
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;
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; RV64I-MO-LABEL: name: funcE
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0
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; RV64I-MO-NEXT: $x11 = ORI $x11, 1023
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4
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; RV64I-MO-NEXT: $x12 = ADDI $x10, 17
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8
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; RV64I-MO-NEXT: $x11 = AND $x12, $x11
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12
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; RV64I-MO-NEXT: $x10 = SUB $x10, $x11
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; RV64I-MO-NEXT: $x10 = ADDI $x10, 1
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -4
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -8
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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$x10 = ADDI $x10, 1
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PseudoRET
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...
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---
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name: funcF
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: funcF
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0
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; RV32I-MO-NEXT: $x11 = ORI $x11, 1023
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4
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; RV32I-MO-NEXT: $x12 = ADDI $x10, 17
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8
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; RV32I-MO-NEXT: $x11 = AND $x12, $x11
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; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12
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; RV32I-MO-NEXT: $x10 = SUB $x10, $x11
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; RV32I-MO-NEXT: $x10 = ADDI $x10, 2
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; RV32I-MO-NEXT: PseudoRET
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;
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; RV64I-MO-LABEL: name: funcF
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0
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; RV64I-MO-NEXT: $x11 = ORI $x11, 1023
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4
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; RV64I-MO-NEXT: $x12 = ADDI $x10, 17
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8
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; RV64I-MO-NEXT: $x11 = AND $x12, $x11
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; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12
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; RV64I-MO-NEXT: $x10 = SUB $x10, $x11
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; RV64I-MO-NEXT: $x10 = ADDI $x10, 2
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -4
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -8
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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$x10 = ADDI $x10, 2
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PseudoRET
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...
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# OUTLINED-LABEL: name: OUTLINED_FUNCTION_0
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# OUTLINED: liveins: $x11, $x10
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# OUTLINED-NEXT: {{ $}}
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# OUTLINED-NEXT: $x10 = ORI $x10, 1023
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# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, 0
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# OUTLINED-NEXT: $x11 = ORI $x11, 1023
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# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -4
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# OUTLINED-NEXT: $x12 = ADDI $x10, 17
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# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -8
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# OUTLINED-NEXT: $x11 = AND $x12, $x11
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# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -12
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# OUTLINED-NEXT: $x10 = SUB $x10, $x11
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# OUTLINED-NEXT: PseudoRET
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