derek.holloway
7502bf64a4
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279 lines
6.4 KiB
LLVM
279 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32
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; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64
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define signext i32 @test1(i32 signext %x) nounwind {
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; RV32-LABEL: test1:
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; RV32: # %bb.0:
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; RV32-NEXT: ori a0, a0, 31
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; RV32-NEXT: slli a0, a0, 10
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test1:
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; RV64: # %bb.0:
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; RV64-NEXT: ori a0, a0, 31
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; RV64-NEXT: slliw a0, a0, 10
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; RV64-NEXT: ret
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%or = shl i32 %x, 10
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%shl = or i32 %or, 31744
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ret i32 %shl
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}
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define signext i32 @test2(i32 signext %x) nounwind {
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; RV32-LABEL: test2:
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; RV32: # %bb.0:
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; RV32-NEXT: xori a0, a0, 31
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; RV32-NEXT: slli a0, a0, 10
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test2:
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; RV64: # %bb.0:
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; RV64-NEXT: xori a0, a0, 31
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; RV64-NEXT: slliw a0, a0, 10
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; RV64-NEXT: ret
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%xor = shl i32 %x, 10
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%shl = xor i32 %xor, 31744
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ret i32 %shl
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}
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define i64 @test3(i64 %x) nounwind {
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; RV32-LABEL: test3:
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; RV32: # %bb.0:
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; RV32-NEXT: andi a1, a0, 241
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; RV32-NEXT: slli a1, a1, 8
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test3:
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; RV64: # %bb.0:
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; RV64-NEXT: andi a0, a0, 241
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; RV64-NEXT: slli a0, a0, 40
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; RV64-NEXT: ret
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%and = shl i64 %x, 40
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%shl = and i64 %and, 264982302294016
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ret i64 %shl
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}
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define i64 @test4(i64 %x) nounwind {
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; RV32-LABEL: test4:
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; RV32: # %bb.0:
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; RV32-NEXT: ori a1, a0, 241
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; RV32-NEXT: slli a1, a1, 8
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test4:
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; RV64: # %bb.0:
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; RV64-NEXT: ori a0, a0, 241
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; RV64-NEXT: slli a0, a0, 40
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; RV64-NEXT: ret
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%or = shl i64 %x, 40
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%shl = or i64 %or, 264982302294016
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ret i64 %shl
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}
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define i64 @test5(i64 %x) nounwind {
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; RV32-LABEL: test5:
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; RV32: # %bb.0:
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; RV32-NEXT: ori a1, a0, 31
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; RV32-NEXT: slli a1, a1, 8
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test5:
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; RV64: # %bb.0:
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; RV64-NEXT: ori a0, a0, 31
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; RV64-NEXT: slli a0, a0, 40
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; RV64-NEXT: ret
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%or = shl i64 %x, 40
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%shl = or i64 %or, 34084860461056
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ret i64 %shl
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}
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define i64 @test6(i64 %x) nounwind {
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; RV32-LABEL: test6:
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; RV32: # %bb.0:
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; RV32-NEXT: xori a1, a0, 241
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; RV32-NEXT: slli a1, a1, 8
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test6:
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; RV64: # %bb.0:
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; RV64-NEXT: xori a0, a0, 241
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; RV64-NEXT: slli a0, a0, 40
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; RV64-NEXT: ret
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%xor = shl i64 %x, 40
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%shl = xor i64 %xor, 264982302294016
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ret i64 %shl
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}
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define i64 @test7(i64 %x) nounwind {
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; RV32-LABEL: test7:
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; RV32: # %bb.0:
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; RV32-NEXT: xori a1, a0, 31
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; RV32-NEXT: slli a1, a1, 8
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test7:
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; RV64: # %bb.0:
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; RV64-NEXT: xori a0, a0, 31
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; RV64-NEXT: slli a0, a0, 40
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; RV64-NEXT: ret
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%xor = shl i64 %x, 40
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%shl = xor i64 %xor, 34084860461056
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ret i64 %shl
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}
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define i64 @test8(i64 %x) nounwind {
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; RV32-LABEL: test8:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 1
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; RV32-NEXT: andi a1, a0, -482
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test8:
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; RV64: # %bb.0:
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; RV64-NEXT: andi a0, a0, -241
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; RV64-NEXT: slli a0, a0, 33
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; RV64-NEXT: ret
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%xor = shl i64 %x, 33
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%shl = and i64 %xor, -2070174236672
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ret i64 %shl
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}
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define i64 @test9(i64 %x) nounwind {
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; RV32-LABEL: test9:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 1
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; RV32-NEXT: ori a1, a0, -482
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test9:
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; RV64: # %bb.0:
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; RV64-NEXT: ori a0, a0, -241
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; RV64-NEXT: slli a0, a0, 33
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; RV64-NEXT: ret
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%xor = shl i64 %x, 33
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%shl = or i64 %xor, -2070174236672
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ret i64 %shl
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}
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define i64 @test10(i64 %x) nounwind {
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; RV32-LABEL: test10:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 1
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; RV32-NEXT: xori a1, a0, -482
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test10:
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; RV64: # %bb.0:
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; RV64-NEXT: xori a0, a0, -241
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; RV64-NEXT: slli a0, a0, 33
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; RV64-NEXT: ret
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%xor = shl i64 %x, 33
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%shl = xor i64 %xor, -2070174236672
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ret i64 %shl
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}
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define signext i32 @test11(i32 signext %x) nounwind {
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; RV32-LABEL: test11:
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; RV32: # %bb.0:
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; RV32-NEXT: andi a0, a0, -241
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; RV32-NEXT: slli a0, a0, 17
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test11:
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; RV64: # %bb.0:
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; RV64-NEXT: andi a0, a0, -241
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; RV64-NEXT: slliw a0, a0, 17
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; RV64-NEXT: ret
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%or = shl i32 %x, 17
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%shl = and i32 %or, -31588352
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ret i32 %shl
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}
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define signext i32 @test12(i32 signext %x) nounwind {
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; RV32-LABEL: test12:
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; RV32: # %bb.0:
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; RV32-NEXT: ori a0, a0, -241
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; RV32-NEXT: slli a0, a0, 17
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test12:
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; RV64: # %bb.0:
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; RV64-NEXT: ori a0, a0, -241
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; RV64-NEXT: slli a0, a0, 17
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; RV64-NEXT: ret
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%or = shl i32 %x, 17
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%shl = or i32 %or, -31588352
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ret i32 %shl
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}
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define signext i32 @test13(i32 signext %x) nounwind {
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; RV32-LABEL: test13:
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; RV32: # %bb.0:
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; RV32-NEXT: xori a0, a0, -241
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; RV32-NEXT: slli a0, a0, 17
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test13:
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; RV64: # %bb.0:
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; RV64-NEXT: xori a0, a0, -241
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; RV64-NEXT: slliw a0, a0, 17
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; RV64-NEXT: ret
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%or = shl i32 %x, 17
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%shl = xor i32 %or, -31588352
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ret i32 %shl
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}
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; Negative test. Can't transform because the constant has a 1 in the bits
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; cleared by the shl.
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define signext i32 @test14(i32 signext %x) nounwind {
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; RV32-LABEL: test14:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 10
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; RV32-NEXT: lui a1, 8
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; RV32-NEXT: addi a1, a1, -1027
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; RV32-NEXT: or a0, a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test14:
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; RV64: # %bb.0:
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; RV64-NEXT: slliw a0, a0, 10
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; RV64-NEXT: lui a1, 8
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; RV64-NEXT: addi a1, a1, -1027
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; RV64-NEXT: or a0, a0, a1
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; RV64-NEXT: ret
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%or = shl i32 %x, 10
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%shl = or i32 %or, 31741
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ret i32 %shl
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}
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; Negative test. Can't transform because the constant has a 1 in the bits
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; cleared by the shl.
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define signext i32 @test15(i32 signext %x) nounwind {
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; RV32-LABEL: test15:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 10
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; RV32-NEXT: lui a1, 8
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; RV32-NEXT: addi a1, a1, -515
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test15:
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; RV64: # %bb.0:
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; RV64-NEXT: slliw a0, a0, 10
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; RV64-NEXT: lui a1, 8
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; RV64-NEXT: addi a1, a1, -515
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: ret
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%xor = shl i32 %x, 10
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%shl = xor i32 %xor, 32253
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ret i32 %shl
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}
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