derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
248 lines
8.0 KiB
YAML
248 lines
8.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
|
|
# RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s
|
|
|
|
---
|
|
name: merge_sextw_removed
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $x11, $x12
|
|
|
|
; CHECK-LABEL: name: merge_sextw_removed
|
|
; CHECK: liveins: $x10, $x11, $x12
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
|
|
; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
|
|
; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
|
|
; CHECK-NEXT: [[MERGE:%[0-9]+]]:gpr = MERGE [[ADDW]], [[ADDW1]], [[ADDW2]]
|
|
; CHECK-NEXT: $x10 = COPY [[MERGE]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
%1:gpr = COPY $x11
|
|
%2:gpr = COPY $x12
|
|
; ADDW produces sign-extended results
|
|
%3:gpr = ADDW %0, %1
|
|
%4:gpr = ADDW %1, %2
|
|
%5:gpr = ADDW %0, %2
|
|
%6:gpr = MERGE %3, %4, %5
|
|
%7:gpr = ADDIW %6, 0
|
|
$x10 = COPY %7
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: mvm_sextw_removed
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $x11, $x12
|
|
|
|
; CHECK-LABEL: name: mvm_sextw_removed
|
|
; CHECK: liveins: $x10, $x11, $x12
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
|
|
; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
|
|
; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
|
|
; CHECK-NEXT: [[MVM:%[0-9]+]]:gpr = MVM [[ADDW]], [[ADDW1]], [[ADDW2]]
|
|
; CHECK-NEXT: $x10 = COPY [[MVM]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
%1:gpr = COPY $x11
|
|
%2:gpr = COPY $x12
|
|
%3:gpr = ADDW %0, %1
|
|
%4:gpr = ADDW %1, %2
|
|
%5:gpr = ADDW %0, %2
|
|
%6:gpr = MVM %3, %4, %5
|
|
%7:gpr = ADDIW %6, 0
|
|
$x10 = COPY %7
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: mvmn_sextw_removed
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $x11, $x12
|
|
|
|
; CHECK-LABEL: name: mvmn_sextw_removed
|
|
; CHECK: liveins: $x10, $x11, $x12
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
|
|
; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
|
|
; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
|
|
; CHECK-NEXT: [[MVMN:%[0-9]+]]:gpr = MVMN [[ADDW]], [[ADDW1]], [[ADDW2]]
|
|
; CHECK-NEXT: $x10 = COPY [[MVMN]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
%1:gpr = COPY $x11
|
|
%2:gpr = COPY $x12
|
|
%3:gpr = ADDW %0, %1
|
|
%4:gpr = ADDW %1, %2
|
|
%5:gpr = ADDW %0, %2
|
|
%6:gpr = MVMN %3, %4, %5
|
|
%7:gpr = ADDIW %6, 0
|
|
$x10 = COPY %7
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: merge_sextw_not_removed
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $x11, $x12
|
|
|
|
; CHECK-LABEL: name: merge_sextw_not_removed
|
|
; CHECK: liveins: $x10, $x11, $x12
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
|
|
; CHECK-NEXT: [[MERGE:%[0-9]+]]:gpr = MERGE [[COPY]], [[COPY1]], [[COPY2]]
|
|
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[MERGE]], 0
|
|
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
%1:gpr = COPY $x11
|
|
%2:gpr = COPY $x12
|
|
%3:gpr = MERGE %0, %1, %2
|
|
%4:gpr = ADDIW %3, 0
|
|
$x10 = COPY %4
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: sati_rv64_sextw_removed_imm16
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; CHECK-LABEL: name: sati_rv64_sextw_removed_imm16
|
|
; CHECK: liveins: $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[SATI_RV64_:%[0-9]+]]:gpr = SATI_RV64 [[COPY]], 16, implicit-def $vxsat
|
|
; CHECK-NEXT: $x10 = COPY [[SATI_RV64_]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
; SATI_RV64 with imm=16 saturates to [-2^15, 2^15-1], which is sign-extended
|
|
%1:gpr = SATI_RV64 %0, 16, implicit-def $vxsat
|
|
%2:gpr = ADDIW %1, 0
|
|
$x10 = COPY %2
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: sati_rv64_sextw_removed_imm32
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; CHECK-LABEL: name: sati_rv64_sextw_removed_imm32
|
|
; CHECK: liveins: $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[SATI_RV64_:%[0-9]+]]:gpr = SATI_RV64 [[COPY]], 32, implicit-def $vxsat
|
|
; CHECK-NEXT: $x10 = COPY [[SATI_RV64_]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
; SATI_RV64 with imm=32 saturates to [-2^31, 2^31-1], which is sign-extended
|
|
%1:gpr = SATI_RV64 %0, 32, implicit-def $vxsat
|
|
%2:gpr = ADDIW %1, 0
|
|
$x10 = COPY %2
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: sati_rv64_sextw_not_removed_imm33
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; CHECK-LABEL: name: sati_rv64_sextw_not_removed_imm33
|
|
; CHECK: liveins: $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[SATI_RV64_:%[0-9]+]]:gpr = SATI_RV64 [[COPY]], 33, implicit-def $vxsat
|
|
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SATI_RV64_]], 0
|
|
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
; SATI_RV64 with imm=33 saturates to [-2^32, 2^32-1], which is NOT sign-extended from bit 31
|
|
%1:gpr = SATI_RV64 %0, 33, implicit-def $vxsat
|
|
%2:gpr = ADDIW %1, 0
|
|
$x10 = COPY %2
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: usati_rv64_sextw_removed_imm16
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; CHECK-LABEL: name: usati_rv64_sextw_removed_imm16
|
|
; CHECK: liveins: $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[USATI_RV64_:%[0-9]+]]:gpr = USATI_RV64 [[COPY]], 16, implicit-def $vxsat
|
|
; CHECK-NEXT: $x10 = COPY [[USATI_RV64_]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
; USATI_RV64 with imm=16 saturates to [0, 2^16-1], which is sign-extended (bit 31 is 0)
|
|
%1:gpr = USATI_RV64 %0, 16, implicit-def $vxsat
|
|
%2:gpr = ADDIW %1, 0
|
|
$x10 = COPY %2
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: usati_rv64_sextw_removed_imm31
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; CHECK-LABEL: name: usati_rv64_sextw_removed_imm31
|
|
; CHECK: liveins: $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[USATI_RV64_:%[0-9]+]]:gpr = USATI_RV64 [[COPY]], 31, implicit-def $vxsat
|
|
; CHECK-NEXT: $x10 = COPY [[USATI_RV64_]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
; USATI_RV64 with imm=31 saturates to [0, 2^31-1], which is sign-extended (bit 31 is 0)
|
|
%1:gpr = USATI_RV64 %0, 31, implicit-def $vxsat
|
|
%2:gpr = ADDIW %1, 0
|
|
$x10 = COPY %2
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: usati_rv64_sextw_not_removed_imm32
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; CHECK-LABEL: name: usati_rv64_sextw_not_removed_imm32
|
|
; CHECK: liveins: $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[USATI_RV64_:%[0-9]+]]:gpr = USATI_RV64 [[COPY]], 32, implicit-def $vxsat
|
|
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[USATI_RV64_]], 0
|
|
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
; USATI_RV64 with imm=32 saturates to [0, 2^32-1], which is NOT sign-extended from bit 31
|
|
%1:gpr = USATI_RV64 %0, 32, implicit-def $vxsat
|
|
%2:gpr = ADDIW %1, 0
|
|
$x10 = COPY %2
|
|
PseudoRET
|
|
...
|