TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir

# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# REQUIRES: asserts
# RUN: llc -mtriple riscv64 -start-before=prologepilog -o - \
# RUN:     -verify-machineinstrs %s | FileCheck %s
#
# RUN: llc -mtriple riscv64 -start-before=prologepilog -o /dev/null \
# RUN:     -debug-only=prologepilog -verify-machineinstrs %s 2>&1 \
# RUN:     | FileCheck --check-prefix=DEBUG %s
#
# DEBUG: Adjusting emergency spill slots!
# DEBUG: Adjusting offset of emergency spill slot #4 from -4112 to -8192

# FIXME: The code generated here is incorrect. It stores a0 to 0(sp) before
# sub sp, sp, a0 but restores it after sub sp, sp, a0. We may need to implement
# the target hook saveScavengerRegister to solve it.

--- |
  ; ModuleID = 'reduced.ll'
  source_filename = "frame_layout-1253b1.cpp"
  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
  target triple = "riscv64"

  ; Function Attrs: nounwind
  define weak_odr dso_local void @foo(ptr %ay) nounwind {
  ; CHECK-LABEL: foo:
  ; CHECK:       # %bb.0: # %entry
  ; CHECK-NEXT:    addi sp, sp, -2032
  ; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
  ; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
  ; CHECK-NEXT:    addi s0, sp, 2032
  ; CHECK-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
  ; CHECK-NEXT:    lui a0, 2
  ; CHECK-NEXT:    addi a0, a0, -2032
  ; CHECK-NEXT:    sub sp, sp, a0
  ; CHECK-NEXT:    srli a0, sp, 12
  ; CHECK-NEXT:    slli sp, a0, 12
  ; CHECK-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
  ; CHECK-NEXT:    sd a1, 0(sp) # 8-byte Folded Spill
  ; CHECK-NEXT:    lui a1, 1
  ; CHECK-NEXT:    add a1, sp, a1
  ; CHECK-NEXT:    sd a0, -8(a1)
  ; CHECK-NEXT:    ld a1, 0(sp) # 8-byte Folded Reload
  ; CHECK-NEXT:    call foo
  ; CHECK-NEXT:    addi sp, s0, -2032
  ; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
  ; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
  ; CHECK-NEXT:    addi sp, sp, 2032
  ; CHECK-NEXT:    ret
  entry:
    ret void
  }


...
---
name:            foo
alignment:       2
tracksRegLiveness: false
frameInfo:
  maxAlignment:    4096
stack:
  - { id: 0, size: 8, alignment: 4096 }
  - { id: 1, type: spill-slot, size: 8, alignment: 8 }
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31

    ; This is to store something to the (non-emergency) spill slot %stack.1.
    SD $x10, %stack.1, 0
    ; This is here just to make all the eligible registers live at this point.
    ; This way when we replace the frame index %stack.1 with its actual address
    ; we have to allocate a virtual register to compute it.
    ; A later run of the the register scavenger won't find an available register
    ; either so it will have to spill one to the emergency spill slot.
    PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
    PseudoRET

...
## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
# DEBUG: {{.*}}