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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rv32-merge-non-arg-reg.mir
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=riscv32 -mattr=+zdinx -run-pass=postrapseudos,riscv-move-merge %s -o - | FileCheck %s --check-prefix=ZDINX
# RUN: llc -mtriple=riscv32 -mattr=+experimental-p -run-pass=postrapseudos,riscv-move-merge %s -o - | FileCheck %s --check-prefix=P-EXT
...
---
name: merge_copy_non_arg_reg
tracksRegLiveness: true
body: |
bb.0:
liveins: $x28, $x29
; ZDINX-LABEL: name: merge_copy_non_arg_reg
; ZDINX: liveins: $x28, $x29
; ZDINX-NEXT: {{ $}}
; ZDINX-NEXT: $x6_x7 = FSGNJ_D_IN32X $x28_x29, $x28_x29
; ZDINX-NEXT: PseudoRET implicit $x6
;
; P-EXT-LABEL: name: merge_copy_non_arg_reg
; P-EXT: liveins: $x28, $x29
; P-EXT-NEXT: {{ $}}
; P-EXT-NEXT: $x6_x7 = PADD_DW $x28_x29, $x0_pair
; P-EXT-NEXT: PseudoRET implicit $x6
$x6 = COPY $x28
$x7 = COPY $x29
PseudoRET implicit $x6
...
---
name: merge_copy_non_arg_reg_with_intervening_unrelated_copy
tracksRegLiveness: true
body: |
bb.0:
liveins: $x12, $x28, $x29
; ZDINX-LABEL: name: merge_copy_non_arg_reg_with_intervening_unrelated_copy
; ZDINX: liveins: $x12, $x28, $x29
; ZDINX-NEXT: {{ $}}
; ZDINX-NEXT: $x6_x7 = FSGNJ_D_IN32X $x28_x29, $x28_x29
; ZDINX-NEXT: $x18 = ADDI $x12, 0
; ZDINX-NEXT: PseudoRET implicit $x6
;
; P-EXT-LABEL: name: merge_copy_non_arg_reg_with_intervening_unrelated_copy
; P-EXT: liveins: $x12, $x28, $x29
; P-EXT-NEXT: {{ $}}
; P-EXT-NEXT: $x6_x7 = PADD_DW $x28_x29, $x0_pair
; P-EXT-NEXT: $x18 = ADDI $x12, 0
; P-EXT-NEXT: PseudoRET implicit $x6
$x6 = COPY $x28
$x18 = COPY $x12
$x7 = COPY $x29
PseudoRET implicit $x6
...