derek.holloway
7502bf64a4
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756 lines
20 KiB
LLVM
756 lines
20 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+m,+zbkb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBKB
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define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: pack_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srli a0, a0, 48
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; RV64I-NEXT: slliw a1, a1, 16
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packw a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%shl = and i32 %a, 65535
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%shl1 = shl i32 %b, 16
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%or = or i32 %shl1, %shl
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ret i32 %or
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}
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define signext i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {
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; RV64I-LABEL: pack_i32_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slliw a1, a1, 16
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packw a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%zexta = zext i16 %a to i32
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%zextb = zext i16 %b to i32
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%shl1 = shl i32 %zextb, 16
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%or = or i32 %shl1, %zexta
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ret i32 %or
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}
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; Test case where we don't have a sign_extend_inreg after the or.
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define signext i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 signext %2) {
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; RV64I-LABEL: pack_i32_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 16
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: addw a0, a0, a2
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32_3:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packw a0, a1, a0
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; RV64ZBKB-NEXT: addw a0, a0, a2
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; RV64ZBKB-NEXT: ret
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%4 = zext i16 %0 to i32
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%5 = shl nuw i32 %4, 16
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%6 = zext i16 %1 to i32
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%7 = or i32 %5, %6
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%8 = add i32 %7, %2
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ret i32 %8
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}
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define i64 @pack_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: pack_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: pack a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%shl = and i64 %a, 4294967295
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%shl1 = shl i64 %b, 32
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%or = or i64 %shl1, %shl
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ret i64 %or
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}
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define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: pack_i64_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: pack a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%zexta = zext i32 %a to i64
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%zextb = zext i32 %b to i64
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%shl1 = shl i64 %zextb, 32
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%or = or i64 %shl1, %zexta
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ret i64 %or
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}
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define i64 @pack_i64_3(ptr %0, ptr %1) {
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; RV64I-LABEL: pack_i64_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: lwu a1, 0(a1)
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64_3:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: lw a0, 0(a0)
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; RV64ZBKB-NEXT: lw a1, 0(a1)
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; RV64ZBKB-NEXT: pack a0, a1, a0
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; RV64ZBKB-NEXT: ret
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%3 = load i32, ptr %0, align 4
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%4 = zext i32 %3 to i64
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%5 = shl i64 %4, 32
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%6 = load i32, ptr %1, align 4
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%7 = zext i32 %6 to i64
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%8 = or i64 %5, %7
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ret i64 %8
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}
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define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: packh_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: zext.b a0, a0
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; RV64I-NEXT: slli a1, a1, 56
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; RV64I-NEXT: srli a1, a1, 48
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i32 %a, 255
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%and1 = shl i32 %b, 8
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%shl = and i32 %and1, 65280
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: packh_i32_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: zext.b a0, a0
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; RV64I-NEXT: zext.b a1, a1
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i32_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i32 %a, 255
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%and1 = and i32 %b, 255
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%shl = shl i32 %and1, 8
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i64 @packh_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: packh_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: zext.b a0, a0
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; RV64I-NEXT: slli a1, a1, 56
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; RV64I-NEXT: srli a1, a1, 48
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i64 %a, 255
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%and1 = shl i64 %b, 8
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%shl = and i64 %and1, 65280
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%or = or i64 %shl, %and
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ret i64 %or
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}
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define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: packh_i64_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: zext.b a0, a0
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; RV64I-NEXT: zext.b a1, a1
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i64_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i64 %a, 255
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%and1 = and i64 %b, 255
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%shl = shl i64 %and1, 8
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%or = or i64 %shl, %and
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ret i64 %or
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}
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define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
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; RV64I-LABEL: packh_i16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i16:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%zext = zext i8 %a to i16
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%zext1 = zext i8 %b to i16
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%shl = shl i16 %zext1, 8
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%or = or i16 %shl, %zext
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ret i16 %or
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}
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define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
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; RV64I-LABEL: packh_i16_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: slli a0, a0, 8
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srli a0, a0, 48
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i16_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: add a0, a1, a0
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; RV64ZBKB-NEXT: packh a0, a2, a0
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; RV64ZBKB-NEXT: ret
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%4 = add i8 %1, %0
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%5 = zext i8 %4 to i16
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%6 = shl i16 %5, 8
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%7 = zext i8 %2 to i16
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%8 = or i16 %6, %7
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ret i16 %8
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}
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define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
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; RV64I-LABEL: packh_i16_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: slli a0, a0, 8
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: sh a0, 0(a3)
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i16_3:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: add a0, a1, a0
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; RV64ZBKB-NEXT: packh a0, a2, a0
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; RV64ZBKB-NEXT: sh a0, 0(a3)
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; RV64ZBKB-NEXT: ret
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%4 = add i8 %1, %0
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%5 = zext i8 %4 to i16
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%6 = shl i16 %5, 8
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%7 = zext i8 %2 to i16
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%8 = or i16 %6, %7
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store i16 %8, ptr %p
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ret void
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}
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define i64 @pack_i64_allWUsers(i32 signext %0, i32 signext %1, i32 signext %2) {
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; RV64I-LABEL: pack_i64_allWUsers:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: slli a2, a2, 32
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a2, a2, 32
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64_allWUsers:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: add a0, a1, a0
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; RV64ZBKB-NEXT: pack a0, a2, a0
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; RV64ZBKB-NEXT: ret
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%4 = add i32 %1, %0
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = zext i32 %2 to i64
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%8 = or i64 %6, %7
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ret i64 %8
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}
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define signext i32 @pack_i32_allWUsers(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2) {
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; RV64I-LABEL: pack_i32_allWUsers:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: slliw a0, a0, 16
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32_allWUsers:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: add a0, a1, a0
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; RV64ZBKB-NEXT: packw a0, a2, a0
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; RV64ZBKB-NEXT: ret
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%4 = add i16 %1, %0
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%5 = zext i16 %4 to i32
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%6 = shl i32 %5, 16
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%7 = zext i16 %2 to i32
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%8 = or i32 %6, %7
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ret i32 %8
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}
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define i64 @pack_i64_imm() {
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; RV64I-LABEL: pack_i64_imm:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 65793
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; RV64I-NEXT: addi a0, a0, 16
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; RV64I-NEXT: slli a1, a0, 32
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64_imm:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: lui a0, 65793
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; RV64ZBKB-NEXT: addi a0, a0, 16
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; RV64ZBKB-NEXT: pack a0, a0, a0
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; RV64ZBKB-NEXT: ret
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ret i64 1157442765409226768 ; 0x0101010101010101
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}
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define i32 @zexth_i32(i32 %a) nounwind {
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; RV64I-LABEL: zexth_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srli a0, a0, 48
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: zexth_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: zext.h a0, a0
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; RV64ZBKB-NEXT: ret
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%and = and i32 %a, 65535
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ret i32 %and
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}
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define i64 @zexth_i64(i64 %a) nounwind {
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; RV64I-LABEL: zexth_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srli a0, a0, 48
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: zexth_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: zext.h a0, a0
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; RV64ZBKB-NEXT: ret
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%and = and i64 %a, 65535
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ret i64 %and
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|
}
|
|
|
|
define i32 @zext_i16_to_i32(i16 %a) nounwind {
|
|
; RV64I-LABEL: zext_i16_to_i32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 48
|
|
; RV64I-NEXT: srli a0, a0, 48
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: zext_i16_to_i32:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: zext.h a0, a0
|
|
; RV64ZBKB-NEXT: ret
|
|
%1 = zext i16 %a to i32
|
|
ret i32 %1
|
|
}
|
|
|
|
define i64 @zext_i16_to_i64(i16 %a) nounwind {
|
|
; RV64I-LABEL: zext_i16_to_i64:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 48
|
|
; RV64I-NEXT: srli a0, a0, 48
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: zext_i16_to_i64:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: zext.h a0, a0
|
|
; RV64ZBKB-NEXT: ret
|
|
%1 = zext i16 %a to i64
|
|
ret i64 %1
|
|
}
|
|
|
|
define void @pack_lo_packh_hi_packh(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, ptr %p) nounwind {
|
|
; RV64I-LABEL: pack_lo_packh_hi_packh:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a1, a1, 8
|
|
; RV64I-NEXT: slli a2, a2, 16
|
|
; RV64I-NEXT: slli a3, a3, 24
|
|
; RV64I-NEXT: or a0, a0, a1
|
|
; RV64I-NEXT: or a2, a2, a3
|
|
; RV64I-NEXT: or a0, a0, a2
|
|
; RV64I-NEXT: sw a0, 0(a4)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: pack_lo_packh_hi_packh:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, a0, a1
|
|
; RV64ZBKB-NEXT: packh a1, a2, a3
|
|
; RV64ZBKB-NEXT: packw a0, a0, a1
|
|
; RV64ZBKB-NEXT: sw a0, 0(a4)
|
|
; RV64ZBKB-NEXT: ret
|
|
%a = zext i8 %0 to i32
|
|
%b = zext i8 %1 to i32
|
|
%c = zext i8 %2 to i32
|
|
%d = zext i8 %3 to i32
|
|
%e = shl i32 %b, 8
|
|
%f = shl i32 %c, 16
|
|
%g = shl i32 %d, 24
|
|
%h = or i32 %a, %e
|
|
%i = or i32 %h, %f
|
|
%j = or i32 %i, %g
|
|
store i32 %j, ptr %p
|
|
ret void
|
|
}
|
|
|
|
define void @pack_lo_packh_hi_packh_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, ptr %p) nounwind {
|
|
; RV64I-LABEL: pack_lo_packh_hi_packh_2:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a1, a1, 8
|
|
; RV64I-NEXT: slli a2, a2, 16
|
|
; RV64I-NEXT: slli a3, a3, 24
|
|
; RV64I-NEXT: or a0, a0, a1
|
|
; RV64I-NEXT: or a2, a2, a3
|
|
; RV64I-NEXT: or a0, a2, a0
|
|
; RV64I-NEXT: sw a0, 0(a4)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: pack_lo_packh_hi_packh_2:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, a0, a1
|
|
; RV64ZBKB-NEXT: packh a1, a2, a3
|
|
; RV64ZBKB-NEXT: packw a0, a0, a1
|
|
; RV64ZBKB-NEXT: sw a0, 0(a4)
|
|
; RV64ZBKB-NEXT: ret
|
|
%a = zext i8 %0 to i32
|
|
%b = zext i8 %1 to i32
|
|
%c = zext i8 %2 to i32
|
|
%d = zext i8 %3 to i32
|
|
%e = shl i32 %b, 8
|
|
%f = shl i32 %c, 16
|
|
%g = shl i32 %d, 24
|
|
%h = or i32 %a, %e
|
|
%i = or i32 %g, %h
|
|
%j = or i32 %f, %i
|
|
store i32 %j, ptr %p
|
|
ret void
|
|
}
|
|
|
|
define void @pack_lo_packh_hi_packh_3(i8 %0, i8 %1, i8 %2, i8 %3, ptr %p) nounwind {
|
|
; RV64I-LABEL: pack_lo_packh_hi_packh_3:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: zext.b a0, a0
|
|
; RV64I-NEXT: zext.b a1, a1
|
|
; RV64I-NEXT: zext.b a2, a2
|
|
; RV64I-NEXT: slli a3, a3, 24
|
|
; RV64I-NEXT: slli a1, a1, 8
|
|
; RV64I-NEXT: slli a2, a2, 16
|
|
; RV64I-NEXT: or a0, a3, a0
|
|
; RV64I-NEXT: or a0, a0, a1
|
|
; RV64I-NEXT: or a0, a2, a0
|
|
; RV64I-NEXT: sw a0, 0(a4)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: pack_lo_packh_hi_packh_3:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, a0, a1
|
|
; RV64ZBKB-NEXT: packh a1, a2, a3
|
|
; RV64ZBKB-NEXT: packw a0, a0, a1
|
|
; RV64ZBKB-NEXT: sw a0, 0(a4)
|
|
; RV64ZBKB-NEXT: ret
|
|
%a = zext i8 %0 to i32
|
|
%b = zext i8 %1 to i32
|
|
%c = zext i8 %2 to i32
|
|
%d = zext i8 %3 to i32
|
|
%e = shl i32 %b, 8
|
|
%f = shl i32 %c, 16
|
|
%g = shl i32 %d, 24
|
|
%h = or i32 %a, %e
|
|
%i = or i32 %g, %h
|
|
%j = or i32 %f, %i
|
|
store i32 %j, ptr %p
|
|
ret void
|
|
}
|
|
|
|
define i32 @pack_lo_packh_hi_packh_4(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, ptr %p) nounwind {
|
|
; RV64I-LABEL: pack_lo_packh_hi_packh_4:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a1, a1, 8
|
|
; RV64I-NEXT: slli a2, a2, 16
|
|
; RV64I-NEXT: slliw a3, a3, 24
|
|
; RV64I-NEXT: or a0, a0, a1
|
|
; RV64I-NEXT: or a2, a2, a3
|
|
; RV64I-NEXT: or a0, a0, a2
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: pack_lo_packh_hi_packh_4:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, a0, a1
|
|
; RV64ZBKB-NEXT: packh a1, a2, a3
|
|
; RV64ZBKB-NEXT: packw a0, a0, a1
|
|
; RV64ZBKB-NEXT: ret
|
|
%a = zext i8 %0 to i32
|
|
%b = zext i8 %1 to i32
|
|
%c = zext i8 %2 to i32
|
|
%d = zext i8 %3 to i32
|
|
%e = shl i32 %b, 8
|
|
%f = shl i32 %c, 16
|
|
%g = shl i32 %d, 24
|
|
%h = or i32 %a, %e
|
|
%i = or i32 %h, %f
|
|
%j = or i32 %i, %g
|
|
ret i32 %j
|
|
}
|
|
|
|
define void @pack_lo_zext_hi_packh(i16 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) nounwind {
|
|
; RV64I-LABEL: pack_lo_zext_hi_packh:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a1, a1, 16
|
|
; RV64I-NEXT: slli a2, a2, 24
|
|
; RV64I-NEXT: or a1, a2, a1
|
|
; RV64I-NEXT: or a0, a1, a0
|
|
; RV64I-NEXT: sw a0, 0(a3)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: pack_lo_zext_hi_packh:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a1, a1, a2
|
|
; RV64ZBKB-NEXT: packw a0, a0, a1
|
|
; RV64ZBKB-NEXT: sw a0, 0(a3)
|
|
; RV64ZBKB-NEXT: ret
|
|
%a = zext i16 %0 to i32
|
|
%b = zext i8 %1 to i32
|
|
%c = zext i8 %2 to i32
|
|
%d = shl i32 %c, 8
|
|
%e = or i32 %b, %d
|
|
%f = shl i32 %e, 16
|
|
%g = or i32 %f, %a
|
|
store i32 %g, ptr %p
|
|
ret void
|
|
}
|
|
|
|
; Negative test, %a isn't extended so we can't use packw for the outer or, but
|
|
; we can use packh for the high half.
|
|
define void @pack_lo_noext_hi_packh(i32 %a, i8 zeroext %1, i8 zeroext %2, ptr %p) nounwind {
|
|
; RV64I-LABEL: pack_lo_noext_hi_packh:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a1, a1, 16
|
|
; RV64I-NEXT: slli a2, a2, 24
|
|
; RV64I-NEXT: or a1, a2, a1
|
|
; RV64I-NEXT: or a0, a1, a0
|
|
; RV64I-NEXT: sw a0, 0(a3)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: pack_lo_noext_hi_packh:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a1, a1, a2
|
|
; RV64ZBKB-NEXT: slli a1, a1, 16
|
|
; RV64ZBKB-NEXT: or a0, a1, a0
|
|
; RV64ZBKB-NEXT: sw a0, 0(a3)
|
|
; RV64ZBKB-NEXT: ret
|
|
%b = zext i8 %1 to i32
|
|
%c = zext i8 %2 to i32
|
|
%d = shl i32 %c, 8
|
|
%e = or i32 %b, %d
|
|
%f = shl i32 %e, 16
|
|
%g = or i32 %f, %a
|
|
store i32 %g, ptr %p
|
|
ret void
|
|
}
|
|
|
|
; Make sure we can match packh+slli without having the input bytes zero extended.
|
|
define void @pack_i32_lo_noext_hi_packh_nozeroext(i32 %a, i8 %1, i8 %2, ptr %p) nounwind {
|
|
; RV64I-LABEL: pack_i32_lo_noext_hi_packh_nozeroext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: zext.b a1, a1
|
|
; RV64I-NEXT: slli a2, a2, 24
|
|
; RV64I-NEXT: slli a1, a1, 16
|
|
; RV64I-NEXT: or a0, a2, a0
|
|
; RV64I-NEXT: or a0, a0, a1
|
|
; RV64I-NEXT: sw a0, 0(a3)
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: pack_i32_lo_noext_hi_packh_nozeroext:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a1, a1, a2
|
|
; RV64ZBKB-NEXT: slli a1, a1, 16
|
|
; RV64ZBKB-NEXT: or a0, a1, a0
|
|
; RV64ZBKB-NEXT: sw a0, 0(a3)
|
|
; RV64ZBKB-NEXT: ret
|
|
%b = zext i8 %1 to i32
|
|
%c = zext i8 %2 to i32
|
|
%d = shl i32 %c, 8
|
|
%e = or i32 %b, %d
|
|
%f = shl i32 %e, 16
|
|
%g = or i32 %f, %a
|
|
store i32 %g, ptr %p
|
|
ret void
|
|
}
|
|
|
|
; Make sure we can match packh+slli without having the input bytes zero extended.
|
|
define i64 @pack_i64_lo_noext_hi_packh_nozeroext(i64 %a, i8 %1, i8 %2, ptr %p) nounwind {
|
|
; RV64I-LABEL: pack_i64_lo_noext_hi_packh_nozeroext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: zext.b a1, a1
|
|
; RV64I-NEXT: zext.b a2, a2
|
|
; RV64I-NEXT: slli a1, a1, 16
|
|
; RV64I-NEXT: slli a2, a2, 24
|
|
; RV64I-NEXT: or a1, a2, a1
|
|
; RV64I-NEXT: or a0, a1, a0
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: pack_i64_lo_noext_hi_packh_nozeroext:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a1, a1, a2
|
|
; RV64ZBKB-NEXT: slli a1, a1, 16
|
|
; RV64ZBKB-NEXT: or a0, a1, a0
|
|
; RV64ZBKB-NEXT: ret
|
|
%b = zext i8 %1 to i64
|
|
%c = zext i8 %2 to i64
|
|
%d = shl i64 %c, 8
|
|
%e = or i64 %b, %d
|
|
%f = shl i64 %e, 16
|
|
%g = or i64 %f, %a
|
|
ret i64 %g
|
|
}
|
|
|
|
define i32 @packh_zero_i32(i32 %a) nounwind {
|
|
; RV64I-LABEL: packh_zero_i32:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 56
|
|
; RV64I-NEXT: srli a0, a0, 48
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: packh_zero_i32:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, zero, a0
|
|
; RV64ZBKB-NEXT: ret
|
|
%shl = shl i32 %a, 8
|
|
%and = and i32 %shl, 65280
|
|
ret i32 %and
|
|
}
|
|
|
|
define i32 @packh_zero_i32_2(i32 %a) nounwind {
|
|
; RV64I-LABEL: packh_zero_i32_2:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: zext.b a0, a0
|
|
; RV64I-NEXT: slli a0, a0, 8
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: packh_zero_i32_2:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, zero, a0
|
|
; RV64ZBKB-NEXT: ret
|
|
%and = and i32 %a, 255
|
|
%shl = shl i32 %and, 8
|
|
ret i32 %shl
|
|
}
|
|
|
|
define i64 @packh_zero_i64(i64 %a) nounwind {
|
|
; RV64I-LABEL: packh_zero_i64:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 56
|
|
; RV64I-NEXT: srli a0, a0, 48
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: packh_zero_i64:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, zero, a0
|
|
; RV64ZBKB-NEXT: ret
|
|
%shl = shl i64 %a, 8
|
|
%and = and i64 %shl, 65280
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @packh_zero_i64_2(i64 %a) nounwind {
|
|
; RV64I-LABEL: packh_zero_i64_2:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: zext.b a0, a0
|
|
; RV64I-NEXT: slli a0, a0, 8
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: packh_zero_i64_2:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, zero, a0
|
|
; RV64ZBKB-NEXT: ret
|
|
%and = and i64 %a, 255
|
|
%shl = shl i64 %and, 8
|
|
ret i64 %shl
|
|
}
|
|
|
|
define i32 @packh_zero_i8(i8 %a) nounwind {
|
|
; RV64I-LABEL: packh_zero_i8:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: zext.b a0, a0
|
|
; RV64I-NEXT: slli a0, a0, 8
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: packh_zero_i8:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: packh a0, zero, a0
|
|
; RV64ZBKB-NEXT: ret
|
|
%zext = zext i8 %a to i32
|
|
%shl = shl i32 %zext, 8
|
|
%and = and i32 %shl, 65280
|
|
ret i32 %and
|
|
}
|
|
|
|
; The 0x0101010101010101 can be materialized with lui+addi+pack
|
|
; The multiply makes the upper 10 bits of the and result unneeded
|
|
; causing the mask to become 0x0001010101010101. Make sure we can still match
|
|
; the lui+addi+pack sequence
|
|
define i64 @and_mul_32bitsplat(i64 %x) {
|
|
; RV64I-LABEL: and_mul_32bitsplat:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: lui a1, 4112
|
|
; RV64I-NEXT: addi a1, a1, 257
|
|
; RV64I-NEXT: slli a2, a1, 32
|
|
; RV64I-NEXT: add a1, a1, a2
|
|
; RV64I-NEXT: lui a2, 65664
|
|
; RV64I-NEXT: addi a2, a2, 1024
|
|
; RV64I-NEXT: and a0, a0, a1
|
|
; RV64I-NEXT: slli a1, a2, 27
|
|
; RV64I-NEXT: add a1, a2, a1
|
|
; RV64I-NEXT: mul a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64ZBKB-LABEL: and_mul_32bitsplat:
|
|
; RV64ZBKB: # %bb.0:
|
|
; RV64ZBKB-NEXT: lui a1, 4112
|
|
; RV64ZBKB-NEXT: lui a2, 65664
|
|
; RV64ZBKB-NEXT: addi a1, a1, 257
|
|
; RV64ZBKB-NEXT: addi a2, a2, 1024
|
|
; RV64ZBKB-NEXT: pack a1, a1, a1
|
|
; RV64ZBKB-NEXT: and a0, a0, a1
|
|
; RV64ZBKB-NEXT: slli a1, a2, 27
|
|
; RV64ZBKB-NEXT: add a1, a2, a1
|
|
; RV64ZBKB-NEXT: mul a0, a0, a1
|
|
; RV64ZBKB-NEXT: ret
|
|
%a = and i64 %x, u0x0101010101010101
|
|
%b = mul i64 %a, u0x0080402010080400
|
|
ret i64 %b
|
|
}
|