derek.holloway
7502bf64a4
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302 lines
9.2 KiB
LLVM
302 lines
9.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
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; RUN: -target-abi lp64 < %s | FileCheck %s -check-prefix=RV64IZHINXMIN
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; This file exhaustively checks half<->i32 conversions.
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define i32 @aext_fptosi(half %a) nounwind {
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; RV64IZFHMIN-LABEL: aext_fptosi:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: aext_fptosi:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
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; RV64IZHINXMIN-NEXT: ret
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%1 = fptosi half %a to i32
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ret i32 %1
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}
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define signext i32 @sext_fptosi(half %a) nounwind {
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; RV64IZFHMIN-LABEL: sext_fptosi:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: sext_fptosi:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
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; RV64IZHINXMIN-NEXT: ret
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%1 = fptosi half %a to i32
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ret i32 %1
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}
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define zeroext i32 @zext_fptosi(half %a) nounwind {
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; RV64IZFHMIN-LABEL: zext_fptosi:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
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; RV64IZFHMIN-NEXT: slli a0, a0, 32
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; RV64IZFHMIN-NEXT: srli a0, a0, 32
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: zext_fptosi:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
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; RV64IZHINXMIN-NEXT: slli a0, a0, 32
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; RV64IZHINXMIN-NEXT: srli a0, a0, 32
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; RV64IZHINXMIN-NEXT: ret
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%1 = fptosi half %a to i32
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ret i32 %1
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}
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define i32 @aext_fptoui(half %a) nounwind {
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; RV64IZFHMIN-LABEL: aext_fptoui:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: aext_fptoui:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
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; RV64IZHINXMIN-NEXT: ret
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%1 = fptoui half %a to i32
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ret i32 %1
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}
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define signext i32 @sext_fptoui(half %a) nounwind {
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; RV64IZFHMIN-LABEL: sext_fptoui:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: sext_fptoui:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
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; RV64IZHINXMIN-NEXT: ret
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%1 = fptoui half %a to i32
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ret i32 %1
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}
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define zeroext i32 @zext_fptoui(half %a) nounwind {
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; RV64IZFHMIN-LABEL: zext_fptoui:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: zext_fptoui:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
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; RV64IZHINXMIN-NEXT: ret
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%1 = fptoui half %a to i32
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ret i32 %1
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}
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define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {
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; RV64IZFHMIN-LABEL: bcvt_f16_to_aext_i16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
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; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
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; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: bcvt_f16_to_aext_i16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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%1 = fadd half %a, %b
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%2 = bitcast half %1 to i16
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ret i16 %2
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}
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define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
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; RV64IZFHMIN-LABEL: bcvt_f16_to_sext_i16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
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; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
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; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: bcvt_f16_to_sext_i16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: slli a0, a0, 48
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; RV64IZHINXMIN-NEXT: srai a0, a0, 48
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; RV64IZHINXMIN-NEXT: ret
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%1 = fadd half %a, %b
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%2 = bitcast half %1 to i16
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ret i16 %2
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}
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define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {
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; RV64IZFHMIN-LABEL: bcvt_f16_to_zext_i16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
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; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
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; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5
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; RV64IZFHMIN-NEXT: slli a0, a0, 48
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; RV64IZFHMIN-NEXT: srli a0, a0, 48
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: bcvt_f16_to_zext_i16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: slli a0, a0, 48
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; RV64IZHINXMIN-NEXT: srli a0, a0, 48
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; RV64IZHINXMIN-NEXT: ret
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%1 = fadd half %a, %b
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%2 = bitcast half %1 to i16
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ret i16 %2
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}
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define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {
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; RV64IZFHMIN-LABEL: bcvt_i64_to_f16_via_i16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fmv.h.x fa5, a0
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; RV64IZFHMIN-NEXT: fmv.h.x fa4, a1
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; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa4
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
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; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
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; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: bcvt_i64_to_f16_via_i16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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%1 = trunc i64 %a to i16
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%2 = trunc i64 %b to i16
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%3 = bitcast i16 %1 to half
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%4 = bitcast i16 %2 to half
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%5 = fadd half %3, %4
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ret half %5
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}
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define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {
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; RV64IZFHMIN-LABEL: uitofp_aext_i32_to_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0
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; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: uitofp_aext_i32_to_f16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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%1 = uitofp i32 %a to half
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ret half %1
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}
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define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {
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; RV64IZFHMIN-LABEL: uitofp_sext_i32_to_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0
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; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: uitofp_sext_i32_to_f16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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%1 = uitofp i32 %a to half
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ret half %1
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}
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define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
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; RV64IZFHMIN-LABEL: uitofp_zext_i32_to_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0
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; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: uitofp_zext_i32_to_f16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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%1 = uitofp i32 %a to half
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ret half %1
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}
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define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
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; RV64IZFHMIN-LABEL: sitofp_aext_i32_to_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0
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; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: sitofp_aext_i32_to_f16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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%1 = sitofp i32 %a to half
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ret half %1
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}
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define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
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; RV64IZFHMIN-LABEL: sitofp_sext_i32_to_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0
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; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: sitofp_sext_i32_to_f16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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%1 = sitofp i32 %a to half
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ret half %1
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}
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define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
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; RV64IZFHMIN-LABEL: sitofp_zext_i32_to_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0
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; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: sitofp_zext_i32_to_f16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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%1 = sitofp i32 %a to half
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ret half %1
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}
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