derek.holloway
7502bf64a4
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832 lines
30 KiB
LLVM
832 lines
30 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+experimental-zvabd -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD
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; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+experimental-zvabd -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD
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define <vscale x 1 x i8> @vp_abs_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv1i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv1i8:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
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ret <vscale x 1 x i8> %v
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}
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define <vscale x 1 x i8> @vp_abs_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv1i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv1i8_unmasked:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 1 x i8> %v
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}
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define <vscale x 2 x i8> @vp_abs_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv2i8:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 2 x i8> @vp_abs_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv2i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv2i8_unmasked:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 4 x i8> @vp_abs_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv4i8:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
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ret <vscale x 4 x i8> %v
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}
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define <vscale x 4 x i8> @vp_abs_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv4i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv4i8_unmasked:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 4 x i8> %v
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}
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define <vscale x 8 x i8> @vp_abs_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv8i8:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
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ret <vscale x 8 x i8> %v
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}
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define <vscale x 8 x i8> @vp_abs_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv8i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv8i8_unmasked:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 8 x i8> %v
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}
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define <vscale x 16 x i8> @vp_abs_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v10, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v10
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv16i8:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
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ret <vscale x 16 x i8> %v
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}
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define <vscale x 16 x i8> @vp_abs_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv16i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v10, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v10
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv16i8_unmasked:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 16 x i8> %v
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}
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define <vscale x 32 x i8> @vp_abs_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v12, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v12
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv32i8:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
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ret <vscale x 32 x i8> %v
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}
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define <vscale x 32 x i8> @vp_abs_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv32i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v12, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v12
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv32i8_unmasked:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 32 x i8> %v
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}
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define <vscale x 64 x i8> @vp_abs_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv64i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; CHECK-NEXT: vrsub.vi v16, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v16
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv64i8:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
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ret <vscale x 64 x i8> %v
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}
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define <vscale x 64 x i8> @vp_abs_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv64i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; CHECK-NEXT: vrsub.vi v16, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v16
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv64i8_unmasked:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 64 x i8> %v
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}
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define <vscale x 1 x i16> @vp_abs_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv1i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv1i16:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
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ret <vscale x 1 x i16> %v
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}
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define <vscale x 1 x i16> @vp_abs_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_abs_nxv1i16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vrsub.vi v9, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v9
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; CHECK-NEXT: ret
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;
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; ZVABD-LABEL: vp_abs_nxv1i16_unmasked:
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; ZVABD: # %bb.0:
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; ZVABD-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; ZVABD-NEXT: vabs.v v8, v8
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; ZVABD-NEXT: ret
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%v = call <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 1 x i16> %v
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}
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define <vscale x 2 x i16> @vp_abs_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv2i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv2i16:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
|
|
ret <vscale x 2 x i16> %v
|
|
}
|
|
|
|
define <vscale x 2 x i16> @vp_abs_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv2i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv2i16_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 2 x i16> %v
|
|
}
|
|
|
|
define <vscale x 4 x i16> @vp_abs_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv4i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv4i16:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
|
|
ret <vscale x 4 x i16> %v
|
|
}
|
|
|
|
define <vscale x 4 x i16> @vp_abs_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv4i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv4i16_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 4 x i16> %v
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vp_abs_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v10, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv8i16:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
|
|
ret <vscale x 8 x i16> %v
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vp_abs_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv8i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v10, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv8i16_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 8 x i16> %v
|
|
}
|
|
|
|
define <vscale x 16 x i16> @vp_abs_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv16i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v12, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv16i16:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
|
|
ret <vscale x 16 x i16> %v
|
|
}
|
|
|
|
define <vscale x 16 x i16> @vp_abs_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv16i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v12, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv16i16_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 16 x i16> %v
|
|
}
|
|
|
|
define <vscale x 32 x i16> @vp_abs_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv32i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v16, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv32i16:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
|
|
ret <vscale x 32 x i16> %v
|
|
}
|
|
|
|
define <vscale x 32 x i16> @vp_abs_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv32i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v16, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv32i16_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e16, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 32 x i16> %v
|
|
}
|
|
|
|
define <vscale x 1 x i32> @vp_abs_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv1i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv1i32:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
|
|
ret <vscale x 1 x i32> %v
|
|
}
|
|
|
|
define <vscale x 1 x i32> @vp_abs_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv1i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv1i32_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 1 x i32> %v
|
|
}
|
|
|
|
define <vscale x 2 x i32> @vp_abs_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv2i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv2i32:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
|
|
ret <vscale x 2 x i32> %v
|
|
}
|
|
|
|
define <vscale x 2 x i32> @vp_abs_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv2i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv2i32_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 2 x i32> %v
|
|
}
|
|
|
|
define <vscale x 4 x i32> @vp_abs_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v10, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv4i32:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
|
|
ret <vscale x 4 x i32> %v
|
|
}
|
|
|
|
define <vscale x 4 x i32> @vp_abs_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv4i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v10, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv4i32_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 4 x i32> %v
|
|
}
|
|
|
|
define <vscale x 8 x i32> @vp_abs_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv8i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v12, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv8i32:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, m4, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
|
|
ret <vscale x 8 x i32> %v
|
|
}
|
|
|
|
define <vscale x 8 x i32> @vp_abs_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv8i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v12, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv8i32_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, m4, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 8 x i32> %v
|
|
}
|
|
|
|
define <vscale x 16 x i32> @vp_abs_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv16i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v16, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv16i32:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
|
|
ret <vscale x 16 x i32> %v
|
|
}
|
|
|
|
define <vscale x 16 x i32> @vp_abs_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv16i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v16, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv16i32_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e32, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 16 x i32> %v
|
|
}
|
|
|
|
define <vscale x 1 x i64> @vp_abs_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv1i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv1i64:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
|
|
ret <vscale x 1 x i64> %v
|
|
}
|
|
|
|
define <vscale x 1 x i64> @vp_abs_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv1i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v9, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv1i64_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 1 x i64> %v
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vp_abs_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v10, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv2i64:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
|
|
ret <vscale x 2 x i64> %v
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vp_abs_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv2i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v10, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv2i64_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 2 x i64> %v
|
|
}
|
|
|
|
define <vscale x 4 x i64> @vp_abs_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv4i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v12, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv4i64:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
|
|
ret <vscale x 4 x i64> %v
|
|
}
|
|
|
|
define <vscale x 4 x i64> @vp_abs_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv4i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v12, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv4i64_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 4 x i64> %v
|
|
}
|
|
|
|
define <vscale x 7 x i64> @vp_abs_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv7i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v16, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv7i64:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
|
|
ret <vscale x 7 x i64> %v
|
|
}
|
|
|
|
define <vscale x 7 x i64> @vp_abs_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv7i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v16, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv7i64_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 7 x i64> %v
|
|
}
|
|
|
|
define <vscale x 8 x i64> @vp_abs_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv8i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v16, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv8i64:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
|
|
ret <vscale x 8 x i64> %v
|
|
}
|
|
|
|
define <vscale x 8 x i64> @vp_abs_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv8i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v16, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv8i64_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 8 x i64> %v
|
|
}
|
|
|
|
define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv16i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v24, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v24
|
|
; CHECK-NEXT: vrsub.vi v24, v16, 0
|
|
; CHECK-NEXT: vmax.vv v16, v16, v24
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv16i64:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: vabs.v v16, v16
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
|
|
ret <vscale x 16 x i64> %v
|
|
}
|
|
|
|
define <vscale x 16 x i64> @vp_abs_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_abs_nxv16i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vrsub.vi v24, v8, 0
|
|
; CHECK-NEXT: vmax.vv v8, v8, v24
|
|
; CHECK-NEXT: vrsub.vi v24, v16, 0
|
|
; CHECK-NEXT: vmax.vv v16, v16, v24
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVABD-LABEL: vp_abs_nxv16i64_unmasked:
|
|
; ZVABD: # %bb.0:
|
|
; ZVABD-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; ZVABD-NEXT: vabs.v v8, v8
|
|
; ZVABD-NEXT: vabs.v v16, v16
|
|
; ZVABD-NEXT: ret
|
|
%v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 16 x i64> %v
|
|
}
|