derek.holloway
7502bf64a4
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89 lines
3.2 KiB
LLVM
89 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
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; Verify that DAGCombiner collapses a BUILD_VECTOR of sign-extended extract
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; elements into a single vector sign extend. (Generalization of the existing
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; zero-extend fold in convertBuildVecZextToZext.)
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define <4 x i32> @buildvec_sext_extract_v4(<8 x i16> %x) {
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; CHECK-LABEL: buildvec_sext_extract_v4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vsext.vf2 v9, v8
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%e0 = extractelement <8 x i16> %x, i32 0
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%e1 = extractelement <8 x i16> %x, i32 1
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%e2 = extractelement <8 x i16> %x, i32 2
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%e3 = extractelement <8 x i16> %x, i32 3
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%s0 = sext i16 %e0 to i32
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%s1 = sext i16 %e1 to i32
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%s2 = sext i16 %e2 to i32
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%s3 = sext i16 %e3 to i32
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%v0 = insertelement <4 x i32> undef, i32 %s0, i32 0
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%v1 = insertelement <4 x i32> %v0, i32 %s1, i32 1
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%v2 = insertelement <4 x i32> %v1, i32 %s2, i32 2
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%v3 = insertelement <4 x i32> %v2, i32 %s3, i32 3
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ret <4 x i32> %v3
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}
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define <4 x i32> @buildvec_zext_extract_v4(<8 x i16> %x) {
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; CHECK-LABEL: buildvec_zext_extract_v4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vzext.vf2 v9, v8
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%e0 = extractelement <8 x i16> %x, i32 0
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%e1 = extractelement <8 x i16> %x, i32 1
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%e2 = extractelement <8 x i16> %x, i32 2
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%e3 = extractelement <8 x i16> %x, i32 3
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%s0 = zext i16 %e0 to i32
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%s1 = zext i16 %e1 to i32
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%s2 = zext i16 %e2 to i32
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%s3 = zext i16 %e3 to i32
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%v0 = insertelement <4 x i32> undef, i32 %s0, i32 0
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%v1 = insertelement <4 x i32> %v0, i32 %s1, i32 1
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%v2 = insertelement <4 x i32> %v1, i32 %s2, i32 2
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%v3 = insertelement <4 x i32> %v2, i32 %s3, i32 3
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ret <4 x i32> %v3
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}
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; Mixed sign and zero extends must not combine (semantics differ for negative
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; inputs).
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define <4 x i32> @buildvec_mixed_sext_zext_v4(<8 x i16> %x) {
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; CHECK-LABEL: buildvec_mixed_sext_zext_v4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: vslidedown.vi v9, v8, 1
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; CHECK-NEXT: vmv.x.s a1, v9
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; CHECK-NEXT: vslidedown.vi v9, v8, 2
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; CHECK-NEXT: vslidedown.vi v8, v8, 3
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; CHECK-NEXT: lui a2, 16
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; CHECK-NEXT: vmv.x.s a3, v9
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; CHECK-NEXT: vmv.x.s a4, v8
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; CHECK-NEXT: addi a2, a2, -1
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; CHECK-NEXT: and a1, a1, a2
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; CHECK-NEXT: and a2, a4, a2
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a0
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; CHECK-NEXT: vslide1down.vx v8, v8, a1
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; CHECK-NEXT: vslide1down.vx v8, v8, a3
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; CHECK-NEXT: vslide1down.vx v8, v8, a2
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; CHECK-NEXT: ret
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%e0 = extractelement <8 x i16> %x, i32 0
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%e1 = extractelement <8 x i16> %x, i32 1
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%e2 = extractelement <8 x i16> %x, i32 2
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%e3 = extractelement <8 x i16> %x, i32 3
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%s0 = sext i16 %e0 to i32
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%s1 = zext i16 %e1 to i32
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%s2 = sext i16 %e2 to i32
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%s3 = zext i16 %e3 to i32
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%v0 = insertelement <4 x i32> undef, i32 %s0, i32 0
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%v1 = insertelement <4 x i32> %v0, i32 %s1, i32 1
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%v2 = insertelement <4 x i32> %v1, i32 %s2, i32 2
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%v3 = insertelement <4 x i32> %v2, i32 %s3, i32 3
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ret <4 x i32> %v3
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}
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