TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer %s -o - 2>&1 | FileCheck %s

# This test used to crash in the register coalescer when the target would
# return the out-of-bounds CommuteAnyOperandIndex for one of its commutable
# operand indices.

--- |
  target triple = "riscv64"
  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"

  define void @commuted_op_indices() {
    unreachable
  }
...
---
name:            commuted_op_indices
tracksRegLiveness: true
registers:
  - { id: 0, class: vr, preferred-register: '' }
  - { id: 1, class: vrnov0, preferred-register: '' }
  - { id: 2, class: vrnov0, preferred-register: '' }
  - { id: 3, class: vr, preferred-register: '' }
body:             |
  bb.0:
    liveins: $v0, $v1, $v2
    ; CHECK-LABEL: name: commuted_op_indices
    ; CHECK: liveins: $v0, $v1, $v2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrnov0 = COPY $v1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrnov0 = COPY $v2
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[COPY]], [[COPY1]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY [[COPY]]
    ; CHECK-NEXT: dead [[COPY3:%[0-9]+]]:vr = PseudoVSLL_VI_M1 undef [[COPY3]], [[COPY3]], 11, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: $v0 = COPY [[COPY]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:vr = COPY $v0
    %1:vrnov0 = COPY $v1
    %2:vrnov0 = COPY $v2
    %0:vr = PseudoVNMSUB_VV_M1 %0, %1, killed %2, -1, 6, 1, implicit $vl, implicit $vtype
    %3:vr = COPY %0
    %3:vr = PseudoVSLL_VI_M1 undef %3, %3, 11, $noreg, 6, 0, implicit $vl, implicit $vtype
    $v0 = COPY %0
    PseudoRET implicit $v0
...