derek.holloway
7502bf64a4
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262 lines
7.1 KiB
LLVM
262 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=RV32
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; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=RV64
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define i32 @v4i1(<4 x i1> %x) {
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; RV32-LABEL: v4i1:
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; RV32: # %bb.0:
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; RV32-NEXT: mv a1, a0
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; RV32-NEXT: lw a0, 0(a0)
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; RV32-NEXT: lw a2, 8(a1)
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: andi a2, a2, 1
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; RV32-NEXT: bnez a0, .LBB0_3
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: lw a0, 4(a1)
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: beqz a2, .LBB0_4
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; RV32-NEXT: .LBB0_2:
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; RV32-NEXT: seqz a1, a2
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; RV32-NEXT: li a2, 2
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; RV32-NEXT: beq a0, a2, .LBB0_5
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; RV32-NEXT: j .LBB0_6
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; RV32-NEXT: .LBB0_3:
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: bnez a2, .LBB0_2
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; RV32-NEXT: .LBB0_4:
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; RV32-NEXT: lw a1, 12(a1)
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; RV32-NEXT: andi a1, a1, 1
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; RV32-NEXT: seqz a1, a1
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; RV32-NEXT: addi a1, a1, 1
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; RV32-NEXT: li a2, 2
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; RV32-NEXT: bne a0, a2, .LBB0_6
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; RV32-NEXT: .LBB0_5:
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; RV32-NEXT: addi a0, a1, 2
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; RV32-NEXT: .LBB0_6:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4i1:
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; RV64: # %bb.0:
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; RV64-NEXT: mv a1, a0
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; RV64-NEXT: ld a0, 0(a0)
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; RV64-NEXT: ld a2, 16(a1)
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; RV64-NEXT: andi a0, a0, 1
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; RV64-NEXT: andi a2, a2, 1
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; RV64-NEXT: bnez a0, .LBB0_3
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: ld a0, 8(a1)
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; RV64-NEXT: andi a0, a0, 1
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: addi a0, a0, 1
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; RV64-NEXT: beqz a2, .LBB0_4
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; RV64-NEXT: .LBB0_2:
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; RV64-NEXT: seqz a1, a2
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; RV64-NEXT: li a2, 2
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; RV64-NEXT: beq a0, a2, .LBB0_5
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; RV64-NEXT: j .LBB0_6
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; RV64-NEXT: .LBB0_3:
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: bnez a2, .LBB0_2
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; RV64-NEXT: .LBB0_4:
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; RV64-NEXT: ld a1, 24(a1)
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; RV64-NEXT: andi a1, a1, 1
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; RV64-NEXT: seqz a1, a1
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; RV64-NEXT: addi a1, a1, 1
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; RV64-NEXT: li a2, 2
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; RV64-NEXT: bne a0, a2, .LBB0_6
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; RV64-NEXT: .LBB0_5:
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; RV64-NEXT: addi a0, a1, 2
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; RV64-NEXT: .LBB0_6:
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; RV64-NEXT: ret
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%y = call i32 @llvm.experimental.cttz.elts(<4 x i1> %x, i1 false)
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ret i32 %y
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}
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define i32 @v4i32(<4 x i32> %x) {
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; RV32-LABEL: v4i32:
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; RV32: # %bb.0:
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; RV32-NEXT: mv a1, a0
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; RV32-NEXT: lw a0, 0(a0)
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; RV32-NEXT: lw a2, 8(a1)
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; RV32-NEXT: bnez a0, .LBB1_3
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: lw a0, 4(a1)
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: beqz a2, .LBB1_4
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; RV32-NEXT: .LBB1_2:
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; RV32-NEXT: seqz a1, a2
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; RV32-NEXT: li a2, 2
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; RV32-NEXT: beq a0, a2, .LBB1_5
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; RV32-NEXT: j .LBB1_6
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; RV32-NEXT: .LBB1_3:
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: bnez a2, .LBB1_2
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; RV32-NEXT: .LBB1_4:
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; RV32-NEXT: lw a1, 12(a1)
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; RV32-NEXT: seqz a1, a1
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; RV32-NEXT: addi a1, a1, 1
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; RV32-NEXT: li a2, 2
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; RV32-NEXT: bne a0, a2, .LBB1_6
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; RV32-NEXT: .LBB1_5:
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; RV32-NEXT: addi a0, a1, 2
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; RV32-NEXT: .LBB1_6:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4i32:
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; RV64: # %bb.0:
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; RV64-NEXT: mv a1, a0
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; RV64-NEXT: lw a0, 0(a0)
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; RV64-NEXT: lw a2, 16(a1)
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; RV64-NEXT: bnez a0, .LBB1_3
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: lw a0, 8(a1)
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: addi a0, a0, 1
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; RV64-NEXT: beqz a2, .LBB1_4
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; RV64-NEXT: .LBB1_2:
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; RV64-NEXT: seqz a1, a2
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; RV64-NEXT: li a2, 2
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; RV64-NEXT: beq a0, a2, .LBB1_5
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; RV64-NEXT: j .LBB1_6
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; RV64-NEXT: .LBB1_3:
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: bnez a2, .LBB1_2
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; RV64-NEXT: .LBB1_4:
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; RV64-NEXT: lw a1, 24(a1)
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; RV64-NEXT: seqz a1, a1
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; RV64-NEXT: addi a1, a1, 1
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; RV64-NEXT: li a2, 2
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; RV64-NEXT: bne a0, a2, .LBB1_6
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; RV64-NEXT: .LBB1_5:
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; RV64-NEXT: addi a0, a1, 2
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; RV64-NEXT: .LBB1_6:
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; RV64-NEXT: ret
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%y = call i32 @llvm.experimental.cttz.elts(<4 x i32> %x, i1 false)
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ret i32 %y
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}
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define i32 @v4i1_zero_is_poison(<4 x i1> %x) {
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; RV32-LABEL: v4i1_zero_is_poison:
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; RV32: # %bb.0:
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; RV32-NEXT: lw a2, 0(a0)
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; RV32-NEXT: lw a1, 8(a0)
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; RV32-NEXT: andi a2, a2, 1
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; RV32-NEXT: andi a1, a1, 1
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; RV32-NEXT: bnez a2, .LBB2_3
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: lw a0, 4(a0)
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: beqz a1, .LBB2_4
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; RV32-NEXT: .LBB2_2:
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; RV32-NEXT: seqz a1, a1
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; RV32-NEXT: li a2, 2
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; RV32-NEXT: beq a0, a2, .LBB2_5
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; RV32-NEXT: j .LBB2_6
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; RV32-NEXT: .LBB2_3:
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; RV32-NEXT: seqz a0, a2
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; RV32-NEXT: bnez a1, .LBB2_2
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; RV32-NEXT: .LBB2_4:
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; RV32-NEXT: li a1, 1
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; RV32-NEXT: li a2, 2
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; RV32-NEXT: bne a0, a2, .LBB2_6
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; RV32-NEXT: .LBB2_5:
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; RV32-NEXT: addi a0, a1, 2
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; RV32-NEXT: .LBB2_6:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4i1_zero_is_poison:
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; RV64: # %bb.0:
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; RV64-NEXT: ld a2, 0(a0)
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; RV64-NEXT: ld a1, 16(a0)
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; RV64-NEXT: andi a2, a2, 1
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; RV64-NEXT: andi a1, a1, 1
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; RV64-NEXT: bnez a2, .LBB2_3
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: ld a0, 8(a0)
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; RV64-NEXT: andi a0, a0, 1
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: addi a0, a0, 1
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; RV64-NEXT: beqz a1, .LBB2_4
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; RV64-NEXT: .LBB2_2:
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; RV64-NEXT: seqz a1, a1
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; RV64-NEXT: li a2, 2
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; RV64-NEXT: beq a0, a2, .LBB2_5
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; RV64-NEXT: j .LBB2_6
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; RV64-NEXT: .LBB2_3:
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; RV64-NEXT: seqz a0, a2
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; RV64-NEXT: bnez a1, .LBB2_2
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; RV64-NEXT: .LBB2_4:
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; RV64-NEXT: li a1, 1
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; RV64-NEXT: li a2, 2
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; RV64-NEXT: bne a0, a2, .LBB2_6
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; RV64-NEXT: .LBB2_5:
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; RV64-NEXT: addiw a0, a1, 2
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; RV64-NEXT: .LBB2_6:
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; RV64-NEXT: ret
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%y = call i32 @llvm.experimental.cttz.elts(<4 x i1> %x, i1 true)
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ret i32 %y
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}
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define i32 @v4i32_zero_is_poison(<4 x i32> %x) {
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; RV32-LABEL: v4i32_zero_is_poison:
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; RV32: # %bb.0:
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; RV32-NEXT: lw a2, 0(a0)
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; RV32-NEXT: lw a1, 8(a0)
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; RV32-NEXT: bnez a2, .LBB3_3
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: lw a0, 4(a0)
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: beqz a1, .LBB3_4
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; RV32-NEXT: .LBB3_2:
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; RV32-NEXT: seqz a1, a1
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; RV32-NEXT: li a2, 2
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; RV32-NEXT: beq a0, a2, .LBB3_5
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; RV32-NEXT: j .LBB3_6
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; RV32-NEXT: .LBB3_3:
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; RV32-NEXT: seqz a0, a2
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; RV32-NEXT: bnez a1, .LBB3_2
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; RV32-NEXT: .LBB3_4:
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; RV32-NEXT: li a1, 1
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; RV32-NEXT: li a2, 2
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; RV32-NEXT: bne a0, a2, .LBB3_6
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; RV32-NEXT: .LBB3_5:
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; RV32-NEXT: addi a0, a1, 2
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; RV32-NEXT: .LBB3_6:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4i32_zero_is_poison:
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; RV64: # %bb.0:
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; RV64-NEXT: lw a2, 0(a0)
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; RV64-NEXT: lw a1, 16(a0)
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; RV64-NEXT: bnez a2, .LBB3_3
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: lw a0, 8(a0)
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: addi a0, a0, 1
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; RV64-NEXT: beqz a1, .LBB3_4
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; RV64-NEXT: .LBB3_2:
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; RV64-NEXT: seqz a1, a1
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; RV64-NEXT: li a2, 2
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; RV64-NEXT: beq a0, a2, .LBB3_5
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; RV64-NEXT: j .LBB3_6
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; RV64-NEXT: .LBB3_3:
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; RV64-NEXT: seqz a0, a2
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; RV64-NEXT: bnez a1, .LBB3_2
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; RV64-NEXT: .LBB3_4:
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; RV64-NEXT: li a1, 1
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; RV64-NEXT: li a2, 2
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; RV64-NEXT: bne a0, a2, .LBB3_6
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; RV64-NEXT: .LBB3_5:
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; RV64-NEXT: addiw a0, a1, 2
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; RV64-NEXT: .LBB3_6:
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; RV64-NEXT: ret
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%y = call i32 @llvm.experimental.cttz.elts(<4 x i32> %x, i1 true)
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ret i32 %y
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}
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