derek.holloway
7502bf64a4
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1662 lines
57 KiB
LLVM
1662 lines
57 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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define <2 x i8> @vp_ctpop_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: li a0, 51
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vi v8, v8, 15
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.ctpop.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vp_ctpop_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v2i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: li a0, 51
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vi v8, v8, 15
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.ctpop.v2i8(<2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl)
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ret <2 x i8> %v
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}
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define <4 x i8> @vp_ctpop_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: li a0, 51
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vi v8, v8, 15
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.vp.ctpop.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
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ret <4 x i8> %v
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}
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define <4 x i8> @vp_ctpop_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v4i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: li a0, 51
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vi v8, v8, 15
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.vp.ctpop.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x i8> %v
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}
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define <8 x i8> @vp_ctpop_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: li a0, 51
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vi v8, v8, 15
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.vp.ctpop.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl)
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ret <8 x i8> %v
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}
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define <8 x i8> @vp_ctpop_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v8i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: li a0, 51
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vi v8, v8, 15
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.vp.ctpop.v8i8(<8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl)
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ret <8 x i8> %v
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}
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define <16 x i8> @vp_ctpop_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: li a0, 51
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vi v8, v8, 15
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; CHECK-NEXT: ret
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%v = call <16 x i8> @llvm.vp.ctpop.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl)
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ret <16 x i8> %v
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}
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define <16 x i8> @vp_ctpop_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v16i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: li a0, 51
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vi v8, v8, 15
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; CHECK-NEXT: ret
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%v = call <16 x i8> @llvm.vp.ctpop.v16i8(<16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl)
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ret <16 x i8> %v
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}
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define <2 x i16> @vp_ctpop_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: lui a0, 5
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; CHECK-NEXT: addi a0, a0, 1365
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: lui a0, 3
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; CHECK-NEXT: addi a0, a0, 819
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: lui a0, 1
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; CHECK-NEXT: addi a0, a0, -241
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: li a0, 257
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; CHECK-NEXT: vmul.vx v8, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 8
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.vp.ctpop.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl)
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ret <2 x i16> %v
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}
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define <2 x i16> @vp_ctpop_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v2i16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: lui a0, 5
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; CHECK-NEXT: addi a0, a0, 1365
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: lui a0, 3
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; CHECK-NEXT: addi a0, a0, 819
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: lui a0, 1
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; CHECK-NEXT: addi a0, a0, -241
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: li a0, 257
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; CHECK-NEXT: vmul.vx v8, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 8
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.vp.ctpop.v2i16(<2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl)
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ret <2 x i16> %v
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}
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define <4 x i16> @vp_ctpop_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
|
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; CHECK-LABEL: vp_ctpop_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: lui a0, 5
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; CHECK-NEXT: addi a0, a0, 1365
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: lui a0, 3
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; CHECK-NEXT: addi a0, a0, 819
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; CHECK-NEXT: vsub.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v9, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: lui a0, 1
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; CHECK-NEXT: addi a0, a0, -241
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; CHECK-NEXT: vadd.vv v8, v9, v8
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; CHECK-NEXT: vsrl.vi v9, v8, 4
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: li a0, 257
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; CHECK-NEXT: vmul.vx v8, v8, a0
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; CHECK-NEXT: vsrl.vi v8, v8, 8
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; CHECK-NEXT: ret
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%v = call <4 x i16> @llvm.vp.ctpop.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
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ret <4 x i16> %v
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}
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define <4 x i16> @vp_ctpop_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_ctpop_v4i16_unmasked:
|
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: lui a0, 5
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; CHECK-NEXT: addi a0, a0, 1365
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: lui a0, 3
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|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v9, v8, a0
|
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; CHECK-NEXT: vsrl.vi v8, v8, 2
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; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 1
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; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v9, v8
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: li a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 8
|
|
; CHECK-NEXT: ret
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%v = call <4 x i16> @llvm.vp.ctpop.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x i16> %v
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}
|
|
|
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define <8 x i16> @vp_ctpop_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 1
|
|
; CHECK-NEXT: lui a0, 5
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v9, v9, a0
|
|
; CHECK-NEXT: lui a0, 3
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|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v9, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 1
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v9, v8
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: li a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 8
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i16> @llvm.vp.ctpop.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i16> %v
|
|
}
|
|
|
|
define <8 x i16> @vp_ctpop_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v8i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 1
|
|
; CHECK-NEXT: lui a0, 5
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v9, v9, a0
|
|
; CHECK-NEXT: lui a0, 3
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v9, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 1
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v9, v8
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: li a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 8
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i16> @llvm.vp.ctpop.v8i16(<8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i16> %v
|
|
}
|
|
|
|
define <16 x i16> @vp_ctpop_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v16i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v10, v8, 1
|
|
; CHECK-NEXT: lui a0, 5
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v10, v10, a0
|
|
; CHECK-NEXT: lui a0, 3
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v10
|
|
; CHECK-NEXT: vand.vx v10, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 1
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v10, v8
|
|
; CHECK-NEXT: vsrl.vi v10, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v10
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: li a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 8
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i16> @llvm.vp.ctpop.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i16> %v
|
|
}
|
|
|
|
define <16 x i16> @vp_ctpop_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v16i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v10, v8, 1
|
|
; CHECK-NEXT: lui a0, 5
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v10, v10, a0
|
|
; CHECK-NEXT: lui a0, 3
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v10
|
|
; CHECK-NEXT: vand.vx v10, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 1
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v10, v8
|
|
; CHECK-NEXT: vsrl.vi v10, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v10
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: li a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 8
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i16> @llvm.vp.ctpop.v16i16(<16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i16> %v
|
|
}
|
|
|
|
define <2 x i32> @vp_ctpop_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v2i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 1
|
|
; CHECK-NEXT: lui a0, 349525
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v9, v9, a0
|
|
; CHECK-NEXT: lui a0, 209715
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v9, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 61681
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v9, v8
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 4112
|
|
; CHECK-NEXT: addi a0, a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 24
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i32> @llvm.vp.ctpop.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl)
|
|
ret <2 x i32> %v
|
|
}
|
|
|
|
define <2 x i32> @vp_ctpop_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v2i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 1
|
|
; CHECK-NEXT: lui a0, 349525
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v9, v9, a0
|
|
; CHECK-NEXT: lui a0, 209715
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v9, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 61681
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v9, v8
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 4112
|
|
; CHECK-NEXT: addi a0, a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 24
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i32> @llvm.vp.ctpop.v2i32(<2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i32> %v
|
|
}
|
|
|
|
define <4 x i32> @vp_ctpop_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 1
|
|
; CHECK-NEXT: lui a0, 349525
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v9, v9, a0
|
|
; CHECK-NEXT: lui a0, 209715
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v9, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 61681
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v9, v8
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 4112
|
|
; CHECK-NEXT: addi a0, a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 24
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i32> @llvm.vp.ctpop.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
|
|
ret <4 x i32> %v
|
|
}
|
|
|
|
define <4 x i32> @vp_ctpop_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v4i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 1
|
|
; CHECK-NEXT: lui a0, 349525
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v9, v9, a0
|
|
; CHECK-NEXT: lui a0, 209715
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v9, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 61681
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v9, v8
|
|
; CHECK-NEXT: vsrl.vi v9, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v9
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 4112
|
|
; CHECK-NEXT: addi a0, a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 24
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i32> @llvm.vp.ctpop.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i32> %v
|
|
}
|
|
|
|
define <8 x i32> @vp_ctpop_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v8i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v10, v8, 1
|
|
; CHECK-NEXT: lui a0, 349525
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v10, v10, a0
|
|
; CHECK-NEXT: lui a0, 209715
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v10
|
|
; CHECK-NEXT: vand.vx v10, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 61681
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v10, v8
|
|
; CHECK-NEXT: vsrl.vi v10, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v10
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 4112
|
|
; CHECK-NEXT: addi a0, a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 24
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i32> @llvm.vp.ctpop.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i32> %v
|
|
}
|
|
|
|
define <8 x i32> @vp_ctpop_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v8i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v10, v8, 1
|
|
; CHECK-NEXT: lui a0, 349525
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v10, v10, a0
|
|
; CHECK-NEXT: lui a0, 209715
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v10
|
|
; CHECK-NEXT: vand.vx v10, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 61681
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v10, v8
|
|
; CHECK-NEXT: vsrl.vi v10, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v10
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 4112
|
|
; CHECK-NEXT: addi a0, a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 24
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i32> @llvm.vp.ctpop.v8i32(<8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i32> %v
|
|
}
|
|
|
|
define <16 x i32> @vp_ctpop_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v16i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v12, v8, 1
|
|
; CHECK-NEXT: lui a0, 349525
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v12, v12, a0
|
|
; CHECK-NEXT: lui a0, 209715
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v12
|
|
; CHECK-NEXT: vand.vx v12, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 61681
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v12, v8
|
|
; CHECK-NEXT: vsrl.vi v12, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v12
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 4112
|
|
; CHECK-NEXT: addi a0, a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 24
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i32> @llvm.vp.ctpop.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i32> %v
|
|
}
|
|
|
|
define <16 x i32> @vp_ctpop_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_ctpop_v16i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vsrl.vi v12, v8, 1
|
|
; CHECK-NEXT: lui a0, 349525
|
|
; CHECK-NEXT: addi a0, a0, 1365
|
|
; CHECK-NEXT: vand.vx v12, v12, a0
|
|
; CHECK-NEXT: lui a0, 209715
|
|
; CHECK-NEXT: addi a0, a0, 819
|
|
; CHECK-NEXT: vsub.vv v8, v8, v12
|
|
; CHECK-NEXT: vand.vx v12, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 2
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 61681
|
|
; CHECK-NEXT: addi a0, a0, -241
|
|
; CHECK-NEXT: vadd.vv v8, v12, v8
|
|
; CHECK-NEXT: vsrl.vi v12, v8, 4
|
|
; CHECK-NEXT: vadd.vv v8, v8, v12
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: lui a0, 4112
|
|
; CHECK-NEXT: addi a0, a0, 257
|
|
; CHECK-NEXT: vmul.vx v8, v8, a0
|
|
; CHECK-NEXT: vsrl.vi v8, v8, 24
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i32> @llvm.vp.ctpop.v16i32(<16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i32> %v
|
|
}
|
|
|
|
define <2 x i64> @vp_ctpop_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v2i64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vsrl.vi v9, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv.v.x v10, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vand.vv v9, v9, v10
|
|
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv.v.x v10, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v9
|
|
; RV32-NEXT: vand.vv v9, v8, v10
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v10
|
|
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv.v.x v10, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v9, v8
|
|
; RV32-NEXT: vsrl.vi v9, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v9
|
|
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv.v.x v9, a0
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v10
|
|
; RV32-NEXT: vmul.vv v8, v8, v9
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v2i64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV64-NEXT: vsrl.vi v9, v8, 1
|
|
; RV64-NEXT: vand.vx v9, v9, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v9
|
|
; RV64-NEXT: vand.vx v9, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v9, v8
|
|
; RV64-NEXT: vsrl.vi v9, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v9
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <2 x i64> @llvm.vp.ctpop.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)
|
|
ret <2 x i64> %v
|
|
}
|
|
|
|
define <2 x i64> @vp_ctpop_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v2i64_unmasked:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vsrl.vi v9, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv.v.x v10, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vand.vv v9, v9, v10
|
|
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv.v.x v10, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v9
|
|
; RV32-NEXT: vand.vv v9, v8, v10
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v10
|
|
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv.v.x v10, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v9, v8
|
|
; RV32-NEXT: vsrl.vi v9, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v9
|
|
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv.v.x v9, a0
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v10
|
|
; RV32-NEXT: vmul.vv v8, v8, v9
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v2i64_unmasked:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV64-NEXT: vsrl.vi v9, v8, 1
|
|
; RV64-NEXT: vand.vx v9, v9, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v9
|
|
; RV64-NEXT: vand.vx v9, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v9, v8
|
|
; RV64-NEXT: vsrl.vi v9, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v9
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <2 x i64> @llvm.vp.ctpop.v2i64(<2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i64> %v
|
|
}
|
|
|
|
define <4 x i64> @vp_ctpop_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v4i64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vsrl.vi v10, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; RV32-NEXT: vmv.v.x v12, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vand.vv v10, v10, v12
|
|
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; RV32-NEXT: vmv.v.x v12, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v10
|
|
; RV32-NEXT: vand.vv v10, v8, v12
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v12
|
|
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; RV32-NEXT: vmv.v.x v12, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v10, v8
|
|
; RV32-NEXT: vsrl.vi v10, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v10
|
|
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; RV32-NEXT: vmv.v.x v10, a0
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v12
|
|
; RV32-NEXT: vmul.vv v8, v8, v10
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v4i64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV64-NEXT: vsrl.vi v10, v8, 1
|
|
; RV64-NEXT: vand.vx v10, v10, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v10
|
|
; RV64-NEXT: vand.vx v10, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v10, v8
|
|
; RV64-NEXT: vsrl.vi v10, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v10
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <4 x i64> @llvm.vp.ctpop.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
|
|
ret <4 x i64> %v
|
|
}
|
|
|
|
define <4 x i64> @vp_ctpop_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v4i64_unmasked:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vsrl.vi v10, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; RV32-NEXT: vmv.v.x v12, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vand.vv v10, v10, v12
|
|
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; RV32-NEXT: vmv.v.x v12, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v10
|
|
; RV32-NEXT: vand.vv v10, v8, v12
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v12
|
|
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; RV32-NEXT: vmv.v.x v12, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v10, v8
|
|
; RV32-NEXT: vsrl.vi v10, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v10
|
|
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; RV32-NEXT: vmv.v.x v10, a0
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v12
|
|
; RV32-NEXT: vmul.vv v8, v8, v10
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v4i64_unmasked:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV64-NEXT: vsrl.vi v10, v8, 1
|
|
; RV64-NEXT: vand.vx v10, v10, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v10
|
|
; RV64-NEXT: vand.vx v10, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v10, v8
|
|
; RV64-NEXT: vsrl.vi v10, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v10
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <4 x i64> @llvm.vp.ctpop.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i64> %v
|
|
}
|
|
|
|
define <8 x i64> @vp_ctpop_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v8i64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vsrl.vi v12, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vand.vv v12, v12, v16
|
|
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v12
|
|
; RV32-NEXT: vand.vv v12, v8, v16
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v12, v8
|
|
; RV32-NEXT: vsrl.vi v12, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v12
|
|
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; RV32-NEXT: vmv.v.x v12, a0
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vmul.vv v8, v8, v12
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v8i64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV64-NEXT: vsrl.vi v12, v8, 1
|
|
; RV64-NEXT: vand.vx v12, v12, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v12
|
|
; RV64-NEXT: vand.vx v12, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v12, v8
|
|
; RV64-NEXT: vsrl.vi v12, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v12
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i64> %v
|
|
}
|
|
|
|
define <8 x i64> @vp_ctpop_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v8i64_unmasked:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vsrl.vi v12, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vand.vv v12, v12, v16
|
|
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v12
|
|
; RV32-NEXT: vand.vv v12, v8, v16
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v12, v8
|
|
; RV32-NEXT: vsrl.vi v12, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v12
|
|
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; RV32-NEXT: vmv.v.x v12, a0
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vmul.vv v8, v8, v12
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v8i64_unmasked:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV64-NEXT: vsrl.vi v12, v8, 1
|
|
; RV64-NEXT: vand.vx v12, v12, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v12
|
|
; RV64-NEXT: vand.vx v12, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v12, v8
|
|
; RV64-NEXT: vsrl.vi v12, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v12
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i64> %v
|
|
}
|
|
|
|
define <15 x i64> @vp_ctpop_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v15i64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsrl.vi v16, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v24, v16, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v24
|
|
; RV32-NEXT: vand.vv v24, v8, v16
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v24, v8
|
|
; RV32-NEXT: vsrl.vi v24, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vmul.vv v8, v8, v24
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v15i64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vsrl.vi v16, v8, 1
|
|
; RV64-NEXT: vand.vx v16, v16, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v16
|
|
; RV64-NEXT: vand.vx v16, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v16, v8
|
|
; RV64-NEXT: vsrl.vi v16, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v16
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)
|
|
ret <15 x i64> %v
|
|
}
|
|
|
|
define <15 x i64> @vp_ctpop_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v15i64_unmasked:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsrl.vi v16, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v24, v16, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v24
|
|
; RV32-NEXT: vand.vv v24, v8, v16
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v24, v8
|
|
; RV32-NEXT: vsrl.vi v24, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vmul.vv v8, v8, v24
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v15i64_unmasked:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vsrl.vi v16, v8, 1
|
|
; RV64-NEXT: vand.vx v16, v16, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v16
|
|
; RV64-NEXT: vand.vx v16, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v16, v8
|
|
; RV64-NEXT: vsrl.vi v16, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v16
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl)
|
|
ret <15 x i64> %v
|
|
}
|
|
|
|
define <16 x i64> @vp_ctpop_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v16i64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsrl.vi v16, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v24, v16, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v24
|
|
; RV32-NEXT: vand.vv v24, v8, v16
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v24, v8
|
|
; RV32-NEXT: vsrl.vi v24, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vmul.vv v8, v8, v24
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v16i64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vsrl.vi v16, v8, 1
|
|
; RV64-NEXT: vand.vx v16, v16, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v16
|
|
; RV64-NEXT: vand.vx v16, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v16, v8
|
|
; RV64-NEXT: vsrl.vi v16, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v16
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i64> %v
|
|
}
|
|
|
|
define <16 x i64> @vp_ctpop_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v16i64_unmasked:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsrl.vi v16, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v24, v16, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsub.vv v8, v8, v24
|
|
; RV32-NEXT: vand.vv v24, v8, v16
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v16, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vadd.vv v8, v24, v8
|
|
; RV32-NEXT: vsrl.vi v24, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v16
|
|
; RV32-NEXT: vmul.vv v8, v8, v24
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v16i64_unmasked:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vsrl.vi v16, v8, 1
|
|
; RV64-NEXT: vand.vx v16, v16, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v16
|
|
; RV64-NEXT: vand.vx v16, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v16, v8
|
|
; RV64-NEXT: vsrl.vi v16, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v16
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: li a0, 56
|
|
; RV64-NEXT: vsrl.vx v8, v8, a0
|
|
; RV64-NEXT: ret
|
|
%v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i64> %v
|
|
}
|
|
|
|
define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v32i64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -16
|
|
; RV32-NEXT: .cfi_def_cfa_offset 16
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsrl.vi v24, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v0, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v24, v24, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vsrl.vi v24, v16, 1
|
|
; RV32-NEXT: vand.vv v24, v24, v0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a1, a1, 3
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 16
|
|
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vsub.vv v8, v8, v0
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v0, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsub.vv v16, v16, v24
|
|
; RV32-NEXT: vand.vv v24, v8, v0
|
|
; RV32-NEXT: addi a0, sp, 16
|
|
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v24, v16, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vsrl.vi v16, v16, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v0
|
|
; RV32-NEXT: vand.vv v16, v16, v0
|
|
; RV32-NEXT: addi a0, sp, 16
|
|
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vadd.vv v8, v24, v8
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a1, a1, 3
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 16
|
|
; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vadd.vv v16, v24, v16
|
|
; RV32-NEXT: vsrl.vi v24, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v24
|
|
; RV32-NEXT: vsrl.vi v24, v16, 4
|
|
; RV32-NEXT: vadd.vv v16, v16, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v24
|
|
; RV32-NEXT: vand.vv v16, v16, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vmul.vv v8, v8, v24
|
|
; RV32-NEXT: vmul.vv v16, v16, v24
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: vsrl.vx v16, v16, a0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add sp, sp, a0
|
|
; RV32-NEXT: .cfi_def_cfa sp, 16
|
|
; RV32-NEXT: addi sp, sp, 16
|
|
; RV32-NEXT: .cfi_def_cfa_offset 0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v32i64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vsrl.vi v24, v8, 1
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: li a4, 56
|
|
; RV64-NEXT: vand.vx v24, v24, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v24
|
|
; RV64-NEXT: vsrl.vi v24, v16, 1
|
|
; RV64-NEXT: vand.vx v24, v24, a0
|
|
; RV64-NEXT: vsub.vv v16, v16, v24
|
|
; RV64-NEXT: vand.vx v24, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v24, v8
|
|
; RV64-NEXT: vand.vx v24, v16, a1
|
|
; RV64-NEXT: vsrl.vi v16, v16, 2
|
|
; RV64-NEXT: vand.vx v16, v16, a1
|
|
; RV64-NEXT: vadd.vv v16, v24, v16
|
|
; RV64-NEXT: vsrl.vi v24, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v24
|
|
; RV64-NEXT: vsrl.vi v24, v16, 4
|
|
; RV64-NEXT: vadd.vv v16, v16, v24
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vand.vx v16, v16, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: vmul.vx v16, v16, a3
|
|
; RV64-NEXT: vsrl.vx v8, v8, a4
|
|
; RV64-NEXT: vsrl.vx v16, v16, a4
|
|
; RV64-NEXT: ret
|
|
%v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
|
|
ret <32 x i64> %v
|
|
}
|
|
|
|
define <32 x i64> @vp_ctpop_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
|
|
; RV32-LABEL: vp_ctpop_v32i64_unmasked:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -16
|
|
; RV32-NEXT: .cfi_def_cfa_offset 16
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsrl.vi v24, v8, 1
|
|
; RV32-NEXT: lui a0, 349525
|
|
; RV32-NEXT: addi a0, a0, 1365
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v0, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v24, v24, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vsrl.vi v24, v16, 1
|
|
; RV32-NEXT: vand.vv v24, v24, v0
|
|
; RV32-NEXT: lui a0, 209715
|
|
; RV32-NEXT: addi a0, a0, 819
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a1, a1, 3
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 16
|
|
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vsub.vv v8, v8, v0
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v0, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vsub.vv v16, v16, v24
|
|
; RV32-NEXT: vand.vv v24, v8, v0
|
|
; RV32-NEXT: addi a0, sp, 16
|
|
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vsrl.vi v8, v8, 2
|
|
; RV32-NEXT: vand.vv v24, v16, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vsrl.vi v16, v16, 2
|
|
; RV32-NEXT: vand.vv v8, v8, v0
|
|
; RV32-NEXT: vand.vv v16, v16, v0
|
|
; RV32-NEXT: addi a0, sp, 16
|
|
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vadd.vv v8, v24, v8
|
|
; RV32-NEXT: lui a0, 61681
|
|
; RV32-NEXT: addi a0, a0, -241
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a1, a1, 3
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 16
|
|
; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vadd.vv v16, v24, v16
|
|
; RV32-NEXT: vsrl.vi v24, v8, 4
|
|
; RV32-NEXT: vadd.vv v8, v8, v24
|
|
; RV32-NEXT: vsrl.vi v24, v16, 4
|
|
; RV32-NEXT: vadd.vv v16, v16, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: lui a0, 4112
|
|
; RV32-NEXT: addi a0, a0, 257
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vand.vv v8, v8, v24
|
|
; RV32-NEXT: vand.vv v16, v16, v24
|
|
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
|
|
; RV32-NEXT: vmv.v.x v24, a0
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vmul.vv v8, v8, v24
|
|
; RV32-NEXT: vmul.vv v16, v16, v24
|
|
; RV32-NEXT: li a0, 56
|
|
; RV32-NEXT: vsrl.vx v8, v8, a0
|
|
; RV32-NEXT: vsrl.vx v16, v16, a0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add sp, sp, a0
|
|
; RV32-NEXT: .cfi_def_cfa sp, 16
|
|
; RV32-NEXT: addi sp, sp, 16
|
|
; RV32-NEXT: .cfi_def_cfa_offset 0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vp_ctpop_v32i64_unmasked:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vsrl.vi v24, v8, 1
|
|
; RV64-NEXT: lui a0, 349525
|
|
; RV64-NEXT: lui a1, 209715
|
|
; RV64-NEXT: lui a2, 61681
|
|
; RV64-NEXT: lui a3, 4112
|
|
; RV64-NEXT: addi a0, a0, 1365
|
|
; RV64-NEXT: addi a1, a1, 819
|
|
; RV64-NEXT: addi a2, a2, -241
|
|
; RV64-NEXT: addi a3, a3, 257
|
|
; RV64-NEXT: slli a4, a0, 32
|
|
; RV64-NEXT: add a0, a0, a4
|
|
; RV64-NEXT: slli a4, a1, 32
|
|
; RV64-NEXT: add a1, a1, a4
|
|
; RV64-NEXT: slli a4, a2, 32
|
|
; RV64-NEXT: add a2, a2, a4
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: li a4, 56
|
|
; RV64-NEXT: vand.vx v24, v24, a0
|
|
; RV64-NEXT: vsub.vv v8, v8, v24
|
|
; RV64-NEXT: vsrl.vi v24, v16, 1
|
|
; RV64-NEXT: vand.vx v24, v24, a0
|
|
; RV64-NEXT: vsub.vv v16, v16, v24
|
|
; RV64-NEXT: vand.vx v24, v8, a1
|
|
; RV64-NEXT: vsrl.vi v8, v8, 2
|
|
; RV64-NEXT: vand.vx v8, v8, a1
|
|
; RV64-NEXT: vadd.vv v8, v24, v8
|
|
; RV64-NEXT: vand.vx v24, v16, a1
|
|
; RV64-NEXT: vsrl.vi v16, v16, 2
|
|
; RV64-NEXT: vand.vx v16, v16, a1
|
|
; RV64-NEXT: vadd.vv v16, v24, v16
|
|
; RV64-NEXT: vsrl.vi v24, v8, 4
|
|
; RV64-NEXT: vadd.vv v8, v8, v24
|
|
; RV64-NEXT: vsrl.vi v24, v16, 4
|
|
; RV64-NEXT: vadd.vv v16, v16, v24
|
|
; RV64-NEXT: vand.vx v8, v8, a2
|
|
; RV64-NEXT: vand.vx v16, v16, a2
|
|
; RV64-NEXT: vmul.vx v8, v8, a3
|
|
; RV64-NEXT: vmul.vx v16, v16, a3
|
|
; RV64-NEXT: vsrl.vx v8, v8, a4
|
|
; RV64-NEXT: vsrl.vx v16, v16, a4
|
|
; RV64-NEXT: ret
|
|
%v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> splat (i1 true), i32 %evl)
|
|
ret <32 x i64> %v
|
|
}
|