derek.holloway
7502bf64a4
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451 lines
13 KiB
LLVM
451 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s -check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s -check-prefix=RV64
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; FIXED WIDTH
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define i16 @ctz_v4i32(<4 x i32> %a) {
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; RV32-LABEL: ctz_v4i32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vmsne.vi v8, v8, 0
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; RV32-NEXT: vfirst.m a0, v8
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; RV32-NEXT: bgez a0, .LBB0_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: li a0, 4
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; RV32-NEXT: .LBB0_2:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_v4i32:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV64-NEXT: vmsne.vi v8, v8, 0
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; RV64-NEXT: vfirst.m a0, v8
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; RV64-NEXT: bgez a0, .LBB0_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: li a0, 4
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; RV64-NEXT: .LBB0_2:
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; RV64-NEXT: ret
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%res = call i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32> %a, i1 0)
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ret i16 %res
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}
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define i16 @ctz_v2048i1(<2048 x i1> %a) {
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; RV32-LABEL: ctz_v2048i1:
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; RV32: # %bb.0:
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; RV32-NEXT: li a1, 128
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; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
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; RV32-NEXT: vfirst.m a0, v0
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; RV32-NEXT: bltz a0, .LBB1_32
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: vfirst.m a2, v8
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; RV32-NEXT: bltz a2, .LBB1_33
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; RV32-NEXT: .LBB1_2:
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; RV32-NEXT: beq a0, a1, .LBB1_34
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; RV32-NEXT: .LBB1_3:
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; RV32-NEXT: vfirst.m a3, v9
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; RV32-NEXT: bltz a3, .LBB1_35
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; RV32-NEXT: .LBB1_4:
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; RV32-NEXT: vfirst.m a2, v10
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; RV32-NEXT: bltz a2, .LBB1_36
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; RV32-NEXT: .LBB1_5:
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; RV32-NEXT: beq a3, a1, .LBB1_37
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; RV32-NEXT: .LBB1_6:
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; RV32-NEXT: li a2, 256
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; RV32-NEXT: beq a0, a2, .LBB1_38
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; RV32-NEXT: .LBB1_7:
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; RV32-NEXT: vfirst.m a4, v11
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; RV32-NEXT: bltz a4, .LBB1_39
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; RV32-NEXT: .LBB1_8:
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; RV32-NEXT: vfirst.m a3, v12
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; RV32-NEXT: bltz a3, .LBB1_40
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; RV32-NEXT: .LBB1_9:
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; RV32-NEXT: beq a4, a1, .LBB1_41
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; RV32-NEXT: .LBB1_10:
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; RV32-NEXT: vfirst.m a3, v13
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; RV32-NEXT: bltz a3, .LBB1_42
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; RV32-NEXT: .LBB1_11:
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; RV32-NEXT: vfirst.m a5, v14
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; RV32-NEXT: bltz a5, .LBB1_43
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; RV32-NEXT: .LBB1_12:
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; RV32-NEXT: beq a3, a1, .LBB1_44
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; RV32-NEXT: .LBB1_13:
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; RV32-NEXT: beq a4, a2, .LBB1_45
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; RV32-NEXT: .LBB1_14:
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; RV32-NEXT: li a3, 512
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; RV32-NEXT: beq a0, a3, .LBB1_46
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; RV32-NEXT: .LBB1_15:
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; RV32-NEXT: vfirst.m a4, v15
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; RV32-NEXT: bltz a4, .LBB1_47
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; RV32-NEXT: .LBB1_16:
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; RV32-NEXT: vfirst.m a5, v16
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; RV32-NEXT: bltz a5, .LBB1_48
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; RV32-NEXT: .LBB1_17:
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; RV32-NEXT: beq a4, a1, .LBB1_49
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; RV32-NEXT: .LBB1_18:
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; RV32-NEXT: vfirst.m a5, v17
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; RV32-NEXT: bltz a5, .LBB1_50
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; RV32-NEXT: .LBB1_19:
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; RV32-NEXT: vfirst.m a6, v18
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; RV32-NEXT: bltz a6, .LBB1_51
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; RV32-NEXT: .LBB1_20:
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; RV32-NEXT: beq a5, a1, .LBB1_52
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; RV32-NEXT: .LBB1_21:
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; RV32-NEXT: beq a4, a2, .LBB1_53
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; RV32-NEXT: .LBB1_22:
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; RV32-NEXT: vfirst.m a5, v19
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; RV32-NEXT: bltz a5, .LBB1_54
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; RV32-NEXT: .LBB1_23:
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; RV32-NEXT: vfirst.m a6, v20
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; RV32-NEXT: bltz a6, .LBB1_55
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; RV32-NEXT: .LBB1_24:
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; RV32-NEXT: beq a5, a1, .LBB1_56
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; RV32-NEXT: .LBB1_25:
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; RV32-NEXT: vfirst.m a6, v21
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; RV32-NEXT: bltz a6, .LBB1_57
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; RV32-NEXT: .LBB1_26:
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; RV32-NEXT: vfirst.m a7, v22
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; RV32-NEXT: bltz a7, .LBB1_58
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; RV32-NEXT: .LBB1_27:
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; RV32-NEXT: beq a6, a1, .LBB1_59
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; RV32-NEXT: .LBB1_28:
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; RV32-NEXT: beq a5, a2, .LBB1_60
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; RV32-NEXT: .LBB1_29:
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; RV32-NEXT: beq a4, a3, .LBB1_61
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; RV32-NEXT: .LBB1_30:
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; RV32-NEXT: li a1, 1024
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; RV32-NEXT: beq a0, a1, .LBB1_62
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; RV32-NEXT: .LBB1_31:
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; RV32-NEXT: ret
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; RV32-NEXT: .LBB1_32:
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; RV32-NEXT: li a0, 128
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; RV32-NEXT: vfirst.m a2, v8
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; RV32-NEXT: bgez a2, .LBB1_2
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; RV32-NEXT: .LBB1_33:
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; RV32-NEXT: li a2, 128
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; RV32-NEXT: bne a0, a1, .LBB1_3
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; RV32-NEXT: .LBB1_34:
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; RV32-NEXT: addi a0, a2, 128
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; RV32-NEXT: vfirst.m a3, v9
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; RV32-NEXT: bgez a3, .LBB1_4
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; RV32-NEXT: .LBB1_35:
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; RV32-NEXT: li a3, 128
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; RV32-NEXT: vfirst.m a2, v10
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; RV32-NEXT: bgez a2, .LBB1_5
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; RV32-NEXT: .LBB1_36:
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; RV32-NEXT: li a2, 128
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; RV32-NEXT: bne a3, a1, .LBB1_6
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; RV32-NEXT: .LBB1_37:
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; RV32-NEXT: addi a3, a2, 128
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; RV32-NEXT: li a2, 256
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; RV32-NEXT: bne a0, a2, .LBB1_7
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; RV32-NEXT: .LBB1_38:
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; RV32-NEXT: addi a0, a3, 256
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; RV32-NEXT: vfirst.m a4, v11
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; RV32-NEXT: bgez a4, .LBB1_8
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; RV32-NEXT: .LBB1_39:
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; RV32-NEXT: li a4, 128
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; RV32-NEXT: vfirst.m a3, v12
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; RV32-NEXT: bgez a3, .LBB1_9
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; RV32-NEXT: .LBB1_40:
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; RV32-NEXT: li a3, 128
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; RV32-NEXT: bne a4, a1, .LBB1_10
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; RV32-NEXT: .LBB1_41:
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; RV32-NEXT: addi a4, a3, 128
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; RV32-NEXT: vfirst.m a3, v13
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; RV32-NEXT: bgez a3, .LBB1_11
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; RV32-NEXT: .LBB1_42:
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; RV32-NEXT: li a3, 128
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; RV32-NEXT: vfirst.m a5, v14
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; RV32-NEXT: bgez a5, .LBB1_12
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; RV32-NEXT: .LBB1_43:
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; RV32-NEXT: li a5, 128
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; RV32-NEXT: bne a3, a1, .LBB1_13
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; RV32-NEXT: .LBB1_44:
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; RV32-NEXT: addi a3, a5, 128
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; RV32-NEXT: bne a4, a2, .LBB1_14
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; RV32-NEXT: .LBB1_45:
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; RV32-NEXT: addi a4, a3, 256
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; RV32-NEXT: li a3, 512
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; RV32-NEXT: bne a0, a3, .LBB1_15
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; RV32-NEXT: .LBB1_46:
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; RV32-NEXT: addi a0, a4, 512
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; RV32-NEXT: vfirst.m a4, v15
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; RV32-NEXT: bgez a4, .LBB1_16
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; RV32-NEXT: .LBB1_47:
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; RV32-NEXT: li a4, 128
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; RV32-NEXT: vfirst.m a5, v16
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; RV32-NEXT: bgez a5, .LBB1_17
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; RV32-NEXT: .LBB1_48:
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; RV32-NEXT: li a5, 128
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; RV32-NEXT: bne a4, a1, .LBB1_18
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; RV32-NEXT: .LBB1_49:
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; RV32-NEXT: addi a4, a5, 128
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; RV32-NEXT: vfirst.m a5, v17
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; RV32-NEXT: bgez a5, .LBB1_19
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; RV32-NEXT: .LBB1_50:
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; RV32-NEXT: li a5, 128
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; RV32-NEXT: vfirst.m a6, v18
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; RV32-NEXT: bgez a6, .LBB1_20
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; RV32-NEXT: .LBB1_51:
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; RV32-NEXT: li a6, 128
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; RV32-NEXT: bne a5, a1, .LBB1_21
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; RV32-NEXT: .LBB1_52:
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; RV32-NEXT: addi a5, a6, 128
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; RV32-NEXT: bne a4, a2, .LBB1_22
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; RV32-NEXT: .LBB1_53:
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; RV32-NEXT: addi a4, a5, 256
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; RV32-NEXT: vfirst.m a5, v19
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; RV32-NEXT: bgez a5, .LBB1_23
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; RV32-NEXT: .LBB1_54:
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; RV32-NEXT: li a5, 128
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; RV32-NEXT: vfirst.m a6, v20
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; RV32-NEXT: bgez a6, .LBB1_24
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; RV32-NEXT: .LBB1_55:
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; RV32-NEXT: li a6, 128
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; RV32-NEXT: bne a5, a1, .LBB1_25
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; RV32-NEXT: .LBB1_56:
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; RV32-NEXT: addi a5, a6, 128
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; RV32-NEXT: vfirst.m a6, v21
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; RV32-NEXT: bgez a6, .LBB1_26
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; RV32-NEXT: .LBB1_57:
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; RV32-NEXT: li a6, 128
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; RV32-NEXT: vfirst.m a7, v22
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; RV32-NEXT: bgez a7, .LBB1_27
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; RV32-NEXT: .LBB1_58:
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; RV32-NEXT: li a7, 128
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; RV32-NEXT: bne a6, a1, .LBB1_28
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; RV32-NEXT: .LBB1_59:
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; RV32-NEXT: addi a6, a7, 128
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; RV32-NEXT: bne a5, a2, .LBB1_29
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; RV32-NEXT: .LBB1_60:
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; RV32-NEXT: addi a5, a6, 256
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; RV32-NEXT: bne a4, a3, .LBB1_30
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; RV32-NEXT: .LBB1_61:
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; RV32-NEXT: addi a4, a5, 512
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; RV32-NEXT: li a1, 1024
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; RV32-NEXT: bne a0, a1, .LBB1_31
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; RV32-NEXT: .LBB1_62:
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; RV32-NEXT: addi a0, a4, 1024
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_v2048i1:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, 128
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; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma
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; RV64-NEXT: vfirst.m a0, v0
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; RV64-NEXT: bltz a0, .LBB1_32
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: vfirst.m a2, v8
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; RV64-NEXT: bltz a2, .LBB1_33
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; RV64-NEXT: .LBB1_2:
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; RV64-NEXT: beq a0, a1, .LBB1_34
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; RV64-NEXT: .LBB1_3:
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; RV64-NEXT: vfirst.m a3, v9
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; RV64-NEXT: bltz a3, .LBB1_35
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; RV64-NEXT: .LBB1_4:
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; RV64-NEXT: vfirst.m a2, v10
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; RV64-NEXT: bltz a2, .LBB1_36
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; RV64-NEXT: .LBB1_5:
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; RV64-NEXT: beq a3, a1, .LBB1_37
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; RV64-NEXT: .LBB1_6:
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; RV64-NEXT: li a2, 256
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; RV64-NEXT: beq a0, a2, .LBB1_38
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; RV64-NEXT: .LBB1_7:
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; RV64-NEXT: vfirst.m a4, v11
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; RV64-NEXT: bltz a4, .LBB1_39
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; RV64-NEXT: .LBB1_8:
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; RV64-NEXT: vfirst.m a3, v12
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; RV64-NEXT: bltz a3, .LBB1_40
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; RV64-NEXT: .LBB1_9:
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; RV64-NEXT: beq a4, a1, .LBB1_41
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; RV64-NEXT: .LBB1_10:
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; RV64-NEXT: vfirst.m a3, v13
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; RV64-NEXT: bltz a3, .LBB1_42
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; RV64-NEXT: .LBB1_11:
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; RV64-NEXT: vfirst.m a5, v14
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; RV64-NEXT: bltz a5, .LBB1_43
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; RV64-NEXT: .LBB1_12:
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; RV64-NEXT: beq a3, a1, .LBB1_44
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; RV64-NEXT: .LBB1_13:
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; RV64-NEXT: beq a4, a2, .LBB1_45
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; RV64-NEXT: .LBB1_14:
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; RV64-NEXT: li a3, 512
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; RV64-NEXT: beq a0, a3, .LBB1_46
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; RV64-NEXT: .LBB1_15:
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; RV64-NEXT: vfirst.m a4, v15
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; RV64-NEXT: bltz a4, .LBB1_47
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; RV64-NEXT: .LBB1_16:
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; RV64-NEXT: vfirst.m a5, v16
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; RV64-NEXT: bltz a5, .LBB1_48
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; RV64-NEXT: .LBB1_17:
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; RV64-NEXT: beq a4, a1, .LBB1_49
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; RV64-NEXT: .LBB1_18:
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; RV64-NEXT: vfirst.m a5, v17
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; RV64-NEXT: bltz a5, .LBB1_50
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; RV64-NEXT: .LBB1_19:
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; RV64-NEXT: vfirst.m a6, v18
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; RV64-NEXT: bltz a6, .LBB1_51
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; RV64-NEXT: .LBB1_20:
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; RV64-NEXT: beq a5, a1, .LBB1_52
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; RV64-NEXT: .LBB1_21:
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; RV64-NEXT: beq a4, a2, .LBB1_53
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; RV64-NEXT: .LBB1_22:
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; RV64-NEXT: vfirst.m a5, v19
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; RV64-NEXT: bltz a5, .LBB1_54
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; RV64-NEXT: .LBB1_23:
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; RV64-NEXT: vfirst.m a6, v20
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; RV64-NEXT: bltz a6, .LBB1_55
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; RV64-NEXT: .LBB1_24:
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; RV64-NEXT: beq a5, a1, .LBB1_56
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; RV64-NEXT: .LBB1_25:
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; RV64-NEXT: vfirst.m a6, v21
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; RV64-NEXT: bltz a6, .LBB1_57
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; RV64-NEXT: .LBB1_26:
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; RV64-NEXT: vfirst.m a7, v22
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; RV64-NEXT: bltz a7, .LBB1_58
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; RV64-NEXT: .LBB1_27:
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; RV64-NEXT: beq a6, a1, .LBB1_59
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; RV64-NEXT: .LBB1_28:
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; RV64-NEXT: beq a5, a2, .LBB1_60
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; RV64-NEXT: .LBB1_29:
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; RV64-NEXT: beq a4, a3, .LBB1_61
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; RV64-NEXT: .LBB1_30:
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; RV64-NEXT: li a1, 1024
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; RV64-NEXT: beq a0, a1, .LBB1_62
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; RV64-NEXT: .LBB1_31:
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; RV64-NEXT: ret
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; RV64-NEXT: .LBB1_32:
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; RV64-NEXT: li a0, 128
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; RV64-NEXT: vfirst.m a2, v8
|
|
; RV64-NEXT: bgez a2, .LBB1_2
|
|
; RV64-NEXT: .LBB1_33:
|
|
; RV64-NEXT: li a2, 128
|
|
; RV64-NEXT: bne a0, a1, .LBB1_3
|
|
; RV64-NEXT: .LBB1_34:
|
|
; RV64-NEXT: addi a0, a2, 128
|
|
; RV64-NEXT: vfirst.m a3, v9
|
|
; RV64-NEXT: bgez a3, .LBB1_4
|
|
; RV64-NEXT: .LBB1_35:
|
|
; RV64-NEXT: li a3, 128
|
|
; RV64-NEXT: vfirst.m a2, v10
|
|
; RV64-NEXT: bgez a2, .LBB1_5
|
|
; RV64-NEXT: .LBB1_36:
|
|
; RV64-NEXT: li a2, 128
|
|
; RV64-NEXT: bne a3, a1, .LBB1_6
|
|
; RV64-NEXT: .LBB1_37:
|
|
; RV64-NEXT: addi a3, a2, 128
|
|
; RV64-NEXT: li a2, 256
|
|
; RV64-NEXT: bne a0, a2, .LBB1_7
|
|
; RV64-NEXT: .LBB1_38:
|
|
; RV64-NEXT: addi a0, a3, 256
|
|
; RV64-NEXT: vfirst.m a4, v11
|
|
; RV64-NEXT: bgez a4, .LBB1_8
|
|
; RV64-NEXT: .LBB1_39:
|
|
; RV64-NEXT: li a4, 128
|
|
; RV64-NEXT: vfirst.m a3, v12
|
|
; RV64-NEXT: bgez a3, .LBB1_9
|
|
; RV64-NEXT: .LBB1_40:
|
|
; RV64-NEXT: li a3, 128
|
|
; RV64-NEXT: bne a4, a1, .LBB1_10
|
|
; RV64-NEXT: .LBB1_41:
|
|
; RV64-NEXT: addi a4, a3, 128
|
|
; RV64-NEXT: vfirst.m a3, v13
|
|
; RV64-NEXT: bgez a3, .LBB1_11
|
|
; RV64-NEXT: .LBB1_42:
|
|
; RV64-NEXT: li a3, 128
|
|
; RV64-NEXT: vfirst.m a5, v14
|
|
; RV64-NEXT: bgez a5, .LBB1_12
|
|
; RV64-NEXT: .LBB1_43:
|
|
; RV64-NEXT: li a5, 128
|
|
; RV64-NEXT: bne a3, a1, .LBB1_13
|
|
; RV64-NEXT: .LBB1_44:
|
|
; RV64-NEXT: addi a3, a5, 128
|
|
; RV64-NEXT: bne a4, a2, .LBB1_14
|
|
; RV64-NEXT: .LBB1_45:
|
|
; RV64-NEXT: addi a4, a3, 256
|
|
; RV64-NEXT: li a3, 512
|
|
; RV64-NEXT: bne a0, a3, .LBB1_15
|
|
; RV64-NEXT: .LBB1_46:
|
|
; RV64-NEXT: addi a0, a4, 512
|
|
; RV64-NEXT: vfirst.m a4, v15
|
|
; RV64-NEXT: bgez a4, .LBB1_16
|
|
; RV64-NEXT: .LBB1_47:
|
|
; RV64-NEXT: li a4, 128
|
|
; RV64-NEXT: vfirst.m a5, v16
|
|
; RV64-NEXT: bgez a5, .LBB1_17
|
|
; RV64-NEXT: .LBB1_48:
|
|
; RV64-NEXT: li a5, 128
|
|
; RV64-NEXT: bne a4, a1, .LBB1_18
|
|
; RV64-NEXT: .LBB1_49:
|
|
; RV64-NEXT: addi a4, a5, 128
|
|
; RV64-NEXT: vfirst.m a5, v17
|
|
; RV64-NEXT: bgez a5, .LBB1_19
|
|
; RV64-NEXT: .LBB1_50:
|
|
; RV64-NEXT: li a5, 128
|
|
; RV64-NEXT: vfirst.m a6, v18
|
|
; RV64-NEXT: bgez a6, .LBB1_20
|
|
; RV64-NEXT: .LBB1_51:
|
|
; RV64-NEXT: li a6, 128
|
|
; RV64-NEXT: bne a5, a1, .LBB1_21
|
|
; RV64-NEXT: .LBB1_52:
|
|
; RV64-NEXT: addi a5, a6, 128
|
|
; RV64-NEXT: bne a4, a2, .LBB1_22
|
|
; RV64-NEXT: .LBB1_53:
|
|
; RV64-NEXT: addi a4, a5, 256
|
|
; RV64-NEXT: vfirst.m a5, v19
|
|
; RV64-NEXT: bgez a5, .LBB1_23
|
|
; RV64-NEXT: .LBB1_54:
|
|
; RV64-NEXT: li a5, 128
|
|
; RV64-NEXT: vfirst.m a6, v20
|
|
; RV64-NEXT: bgez a6, .LBB1_24
|
|
; RV64-NEXT: .LBB1_55:
|
|
; RV64-NEXT: li a6, 128
|
|
; RV64-NEXT: bne a5, a1, .LBB1_25
|
|
; RV64-NEXT: .LBB1_56:
|
|
; RV64-NEXT: addi a5, a6, 128
|
|
; RV64-NEXT: vfirst.m a6, v21
|
|
; RV64-NEXT: bgez a6, .LBB1_26
|
|
; RV64-NEXT: .LBB1_57:
|
|
; RV64-NEXT: li a6, 128
|
|
; RV64-NEXT: vfirst.m a7, v22
|
|
; RV64-NEXT: bgez a7, .LBB1_27
|
|
; RV64-NEXT: .LBB1_58:
|
|
; RV64-NEXT: li a7, 128
|
|
; RV64-NEXT: bne a6, a1, .LBB1_28
|
|
; RV64-NEXT: .LBB1_59:
|
|
; RV64-NEXT: addi a6, a7, 128
|
|
; RV64-NEXT: bne a5, a2, .LBB1_29
|
|
; RV64-NEXT: .LBB1_60:
|
|
; RV64-NEXT: addi a5, a6, 256
|
|
; RV64-NEXT: bne a4, a3, .LBB1_30
|
|
; RV64-NEXT: .LBB1_61:
|
|
; RV64-NEXT: addi a4, a5, 512
|
|
; RV64-NEXT: li a1, 1024
|
|
; RV64-NEXT: bne a0, a1, .LBB1_31
|
|
; RV64-NEXT: .LBB1_62:
|
|
; RV64-NEXT: addi a0, a4, 1024
|
|
; RV64-NEXT: ret
|
|
%res = call i16 @llvm.experimental.cttz.elts(<2048 x i1> %a, i1 0)
|
|
ret i16 %res
|
|
}
|
|
|
|
; ZERO IS POISON
|
|
|
|
define i32 @ctz_v2i1_poison(<2 x i1> %a) {
|
|
; RV32-LABEL: ctz_v2i1_poison:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
|
|
; RV32-NEXT: vfirst.m a0, v0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: ctz_v2i1_poison:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
|
|
; RV64-NEXT: vfirst.m a0, v0
|
|
; RV64-NEXT: ret
|
|
%res = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> %a, i1 1)
|
|
ret i32 %res
|
|
}
|
|
|