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60 lines
3.0 KiB
YAML
60 lines
3.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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# RUN: llc -mtriple riscv64 -mattr=+v -target-abi=lp64 -start-before=prologepilog -o - \
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# RUN: -verify-machineinstrs %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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define weak_odr dso_local void @fixedlen_vector_spillslot(ptr %ay) nounwind {
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; CHECK-LABEL: fixedlen_vector_spillslot:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -48
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; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd a0, 32(sp)
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; CHECK-NEXT: sd a0, 16(sp)
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
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; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
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; CHECK-NEXT: addi a1, sp, 24
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; CHECK-NEXT: vs1r.v v25, (a1) # vscale x 8-byte Folded Spill
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; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
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; CHECK-NEXT: call fixedlen_vector_spillslot
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; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 48
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; CHECK-NEXT: ret
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entry:
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ret void
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}
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...
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---
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name: fixedlen_vector_spillslot
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alignment: 2
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tracksRegLiveness: false
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fixedStack: []
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stack:
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- { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: 0, size: 2, alignment: 8,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0.entry:
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liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v25
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SD $x10, %stack.0, 0
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SD $x10, %stack.2, 0
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dead $x0 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype
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VS1R_V killed renamable $v25, %stack.1 :: (store (<vscale x 1 x s64>) into %stack.1, align 8)
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; This is here just to make all the eligible registers live at this point.
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; This way when we replace the frame index %stack.1 with its actual address
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; we have to allocate a virtual register to compute it.
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; A later run of the the register scavenger won't find an available register
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; either so it will have to spill one to the emergency spill slot.
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PseudoCALL target-flags(riscv-call) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
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PseudoRET
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...
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