derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
511 lines
20 KiB
LLVM
511 lines
20 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH
|
|
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH
|
|
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN
|
|
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN
|
|
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
|
|
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v \
|
|
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
|
|
|
|
define <2 x bfloat> @vfmin_v2bf16_vv(<2 x bfloat> %a, <2 x bfloat> %b) {
|
|
; ZVFBFMIN-LABEL: vfmin_v2bf16_vv:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
|
|
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
|
|
; ZVFBFMIN-NEXT: vfmin.vv v9, v8, v9
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: vfmin_v2bf16_vv:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
|
|
; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFBFA-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFBFA-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFBFA-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFBFA-NEXT: vfmin.vv v8, v8, v10
|
|
; ZVFBFA-NEXT: ret
|
|
%v = call <2 x bfloat> @llvm.minimum.v2bf16(<2 x bfloat> %a, <2 x bfloat> %b)
|
|
ret <2 x bfloat> %v
|
|
}
|
|
|
|
define <4 x bfloat> @vfmin_v4bf16_vv(<4 x bfloat> %a, <4 x bfloat> %b) {
|
|
; ZVFBFMIN-LABEL: vfmin_v4bf16_vv:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
|
|
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
|
|
; ZVFBFMIN-NEXT: vfmin.vv v9, v8, v9
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: vfmin_v4bf16_vv:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
|
|
; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFBFA-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFBFA-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFBFA-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFBFA-NEXT: vfmin.vv v8, v8, v10
|
|
; ZVFBFA-NEXT: ret
|
|
%v = call <4 x bfloat> @llvm.minimum.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b)
|
|
ret <4 x bfloat> %v
|
|
}
|
|
|
|
define <8 x bfloat> @vfmin_v8bf16_vv(<8 x bfloat> %a, <8 x bfloat> %b) {
|
|
; ZVFBFMIN-LABEL: vfmin_v8bf16_vv:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v9
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v12, v0
|
|
; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
|
|
; ZVFBFMIN-NEXT: vmerge.vvm v10, v12, v10, v0
|
|
; ZVFBFMIN-NEXT: vfmin.vv v10, v10, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: vfmin_v8bf16_vv:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
|
|
; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFBFA-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFBFA-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFBFA-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFBFA-NEXT: vfmin.vv v8, v8, v10
|
|
; ZVFBFA-NEXT: ret
|
|
%v = call <8 x bfloat> @llvm.minimum.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b)
|
|
ret <8 x bfloat> %v
|
|
}
|
|
|
|
define <16 x bfloat> @vfmin_v16bf16_vv(<16 x bfloat> %a, <16 x bfloat> %b) {
|
|
; ZVFBFMIN-LABEL: vfmin_v16bf16_vv:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v10
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v16, v0
|
|
; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
|
|
; ZVFBFMIN-NEXT: vmerge.vvm v12, v16, v12, v0
|
|
; ZVFBFMIN-NEXT: vfmin.vv v12, v12, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: vfmin_v16bf16_vv:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
|
|
; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFBFA-NEXT: vmerge.vvm v12, v8, v10, v0
|
|
; ZVFBFA-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFBFA-NEXT: vmerge.vvm v8, v10, v8, v0
|
|
; ZVFBFA-NEXT: vfmin.vv v8, v8, v12
|
|
; ZVFBFA-NEXT: ret
|
|
%v = call <16 x bfloat> @llvm.minimum.v16bf16(<16 x bfloat> %a, <16 x bfloat> %b)
|
|
ret <16 x bfloat> %v
|
|
}
|
|
|
|
define <2 x half> @vfmin_v2f16_vv(<2 x half> %a, <2 x half> %b) {
|
|
; ZVFH-LABEL: vfmin_v2f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFH-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v10
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmin_v2f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)
|
|
ret <2 x half> %v
|
|
}
|
|
|
|
define <4 x half> @vfmin_v4f16_vv(<4 x half> %a, <4 x half> %b) {
|
|
; ZVFH-LABEL: vfmin_v4f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFH-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v10
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmin_v4f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <4 x half> @llvm.minimum.v4f16(<4 x half> %a, <4 x half> %b)
|
|
ret <4 x half> %v
|
|
}
|
|
|
|
define <8 x half> @vfmin_v8f16_vv(<8 x half> %a, <8 x half> %b) {
|
|
; ZVFH-LABEL: vfmin_v8f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFH-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v10
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmin_v8f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
|
|
; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <8 x half> @llvm.minimum.v8f16(<8 x half> %a, <8 x half> %b)
|
|
ret <8 x half> %v
|
|
}
|
|
|
|
define <16 x half> @vfmin_v16f16_vv(<16 x half> %a, <16 x half> %b) {
|
|
; ZVFH-LABEL: vfmin_v16f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0
|
|
; ZVFH-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v12
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmin_v16f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
|
|
; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <16 x half> @llvm.minimum.v16f16(<16 x half> %a, <16 x half> %b)
|
|
ret <16 x half> %v
|
|
}
|
|
|
|
define <2 x float> @vfmin_v2f32_vv(<2 x float> %a, <2 x float> %b) {
|
|
; CHECK-LABEL: vfmin_v2f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v9, v9
|
|
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x float> @llvm.minimum.v2f32(<2 x float> %a, <2 x float> %b)
|
|
ret <2 x float> %v
|
|
}
|
|
|
|
define <4 x float> @vfmin_v4f32_vv(<4 x float> %a, <4 x float> %b) {
|
|
; CHECK-LABEL: vfmin_v4f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v9, v9
|
|
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)
|
|
ret <4 x float> %v
|
|
}
|
|
|
|
define <8 x float> @vfmin_v8f32_vv(<8 x float> %a, <8 x float> %b) {
|
|
; CHECK-LABEL: vfmin_v8f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v10, v10
|
|
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x float> @llvm.minimum.v8f32(<8 x float> %a, <8 x float> %b)
|
|
ret <8 x float> %v
|
|
}
|
|
|
|
define <16 x float> @vfmin_v16f32_vv(<16 x float> %a, <16 x float> %b) {
|
|
; CHECK-LABEL: vfmin_v16f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v12, v12
|
|
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x float> @llvm.minimum.v16f32(<16 x float> %a, <16 x float> %b)
|
|
ret <16 x float> %v
|
|
}
|
|
|
|
define <2 x double> @vfmin_v2f64_vv(<2 x double> %a, <2 x double> %b) {
|
|
; CHECK-LABEL: vfmin_v2f64_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v9, v9
|
|
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b)
|
|
ret <2 x double> %v
|
|
}
|
|
|
|
define <4 x double> @vfmin_v4f64_vv(<4 x double> %a, <4 x double> %b) {
|
|
; CHECK-LABEL: vfmin_v4f64_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v10, v10
|
|
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x double> @llvm.minimum.v4f64(<4 x double> %a, <4 x double> %b)
|
|
ret <4 x double> %v
|
|
}
|
|
|
|
define <8 x double> @vfmin_v8f64_vv(<8 x double> %a, <8 x double> %b) {
|
|
; CHECK-LABEL: vfmin_v8f64_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v12, v12
|
|
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x double> @llvm.minimum.v8f64(<8 x double> %a, <8 x double> %b)
|
|
ret <8 x double> %v
|
|
}
|
|
|
|
define <16 x double> @vfmin_v16f64_vv(<16 x double> %a, <16 x double> %b) nounwind {
|
|
; CHECK-LABEL: vfmin_v16f64_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmfeq.vv v7, v16, v16
|
|
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v24
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x double> @llvm.minimum.v16f64(<16 x double> %a, <16 x double> %b)
|
|
ret <16 x double> %v
|
|
}
|
|
|
|
define <2 x half> @vfmin_v2f16_vv_nnan(<2 x half> %a, <2 x half> %b) {
|
|
; ZVFH-LABEL: vfmin_v2f16_vv_nnan:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v9
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnan:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call nnan <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)
|
|
ret <2 x half> %v
|
|
}
|
|
|
|
define <2 x half> @vfmin_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) {
|
|
; ZVFH-LABEL: vfmin_v2f16_vv_nnana:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
|
|
; ZVFH-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFH-NEXT: vmv1r.v v10, v9
|
|
; ZVFH-NEXT: vfadd.vv v10, v8, v8, v0.t
|
|
; ZVFH-NEXT: vfmin.vv v8, v10, v9
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnana:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v9, v10, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%c = fadd nnan <2 x half> %a, %a
|
|
%v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %c, <2 x half> %b)
|
|
ret <2 x half> %v
|
|
}
|
|
|
|
define <2 x half> @vfmin_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {
|
|
; ZVFH-LABEL: vfmin_v2f16_vv_nnanb:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmv1r.v v10, v8
|
|
; ZVFH-NEXT: vfadd.vv v10, v9, v9, v0.t
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v10
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnanb:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v10, v9, v8, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%c = fadd nnan <2 x half> %b, %b
|
|
%v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %c)
|
|
ret <2 x half> %v
|
|
}
|
|
|
|
define <4 x half> @vfmin_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half> %b, <4 x half> %c) {
|
|
; ZVFH-LABEL: vfmin_v2f16_vv_nnan_insert_subvector:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vfadd.vv v8, v8, v8
|
|
; ZVFH-NEXT: vfadd.vv v9, v9, v9
|
|
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFH-NEXT: vslideup.vi v8, v9, 2
|
|
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v10
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnan_insert_subvector:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfadd.vv v9, v11, v11
|
|
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v9
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vslideup.vi v11, v9, 2
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%d = fadd nnan <2 x half> %a, %a
|
|
%e = fadd nnan <2 x half> %b, %b
|
|
%f = call <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half> poison, <2 x half> %d, i64 0)
|
|
%g = call <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half> %f, <2 x half> %e, i64 2)
|
|
%v = call <4 x half> @llvm.minimum.v4f16(<4 x half> %g, <4 x half> %c)
|
|
ret <4 x half> %v
|
|
}
|