derek.holloway
7502bf64a4
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187 lines
7.0 KiB
LLVM
187 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFBFMIN,RV32-NO-ZFBFMIN
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFBFMIN,RV64-NO-ZFBFMIN
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFBFMIN,RV32-ZFBFMIN
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFBFMIN,RV64-ZFBFMIN
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFBFA
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFBFA
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define <4 x bfloat> @splat_idx_v4bf16(<4 x bfloat> %v, i64 %idx) {
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; RV32-NO-ZFBFMIN-LABEL: splat_idx_v4bf16:
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; RV32-NO-ZFBFMIN: # %bb.0:
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; RV32-NO-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; RV32-NO-ZFBFMIN-NEXT: vrgather.vx v9, v8, a0
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; RV32-NO-ZFBFMIN-NEXT: vmv1r.v v8, v9
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; RV32-NO-ZFBFMIN-NEXT: ret
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;
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; RV64-NO-ZFBFMIN-LABEL: splat_idx_v4bf16:
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; RV64-NO-ZFBFMIN: # %bb.0:
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; RV64-NO-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; RV64-NO-ZFBFMIN-NEXT: vrgather.vx v9, v8, a0
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; RV64-NO-ZFBFMIN-NEXT: vmv1r.v v8, v9
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; RV64-NO-ZFBFMIN-NEXT: ret
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;
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; RV32-ZFBFMIN-LABEL: splat_idx_v4bf16:
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; RV32-ZFBFMIN: # %bb.0:
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; RV32-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; RV32-ZFBFMIN-NEXT: vslidedown.vx v8, v8, a0
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; RV32-ZFBFMIN-NEXT: vmv.x.s a0, v8
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; RV32-ZFBFMIN-NEXT: vmv.v.x v8, a0
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; RV32-ZFBFMIN-NEXT: ret
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;
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; RV64-ZFBFMIN-LABEL: splat_idx_v4bf16:
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; RV64-ZFBFMIN: # %bb.0:
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; RV64-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; RV64-ZFBFMIN-NEXT: vslidedown.vx v8, v8, a0
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; RV64-ZFBFMIN-NEXT: vmv.x.s a0, v8
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; RV64-ZFBFMIN-NEXT: vmv.v.x v8, a0
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; RV64-ZFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: splat_idx_v4bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFBFA-NEXT: vrgather.vx v9, v8, a0
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; ZVFBFA-NEXT: vmv1r.v v8, v9
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; ZVFBFA-NEXT: ret
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%x = extractelement <4 x bfloat> %v, i64 %idx
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%ins = insertelement <4 x bfloat> poison, bfloat %x, i32 0
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%splat = shufflevector <4 x bfloat> %ins, <4 x bfloat> poison, <4 x i32> zeroinitializer
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ret <4 x bfloat> %splat
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}
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define <2 x bfloat> @buildvec_v2bf16(bfloat %a, bfloat %b) {
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; RV32-NO-ZFBFMIN-LABEL: buildvec_v2bf16:
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; RV32-NO-ZFBFMIN: # %bb.0:
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; RV32-NO-ZFBFMIN-NEXT: fmv.x.w a0, fa1
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; RV32-NO-ZFBFMIN-NEXT: fmv.x.w a1, fa0
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; RV32-NO-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; RV32-NO-ZFBFMIN-NEXT: vmv.v.x v8, a1
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; RV32-NO-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0
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; RV32-NO-ZFBFMIN-NEXT: ret
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;
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; RV64-NO-ZFBFMIN-LABEL: buildvec_v2bf16:
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; RV64-NO-ZFBFMIN: # %bb.0:
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; RV64-NO-ZFBFMIN-NEXT: fmv.x.w a0, fa1
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; RV64-NO-ZFBFMIN-NEXT: fmv.x.w a1, fa0
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; RV64-NO-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; RV64-NO-ZFBFMIN-NEXT: vmv.v.x v8, a1
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; RV64-NO-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0
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; RV64-NO-ZFBFMIN-NEXT: ret
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;
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; RV32-ZFBFMIN-LABEL: buildvec_v2bf16:
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; RV32-ZFBFMIN: # %bb.0:
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; RV32-ZFBFMIN-NEXT: fmv.x.h a0, fa1
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; RV32-ZFBFMIN-NEXT: fmv.x.h a1, fa0
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; RV32-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; RV32-ZFBFMIN-NEXT: vmv.v.x v8, a1
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; RV32-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0
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; RV32-ZFBFMIN-NEXT: ret
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;
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; RV64-ZFBFMIN-LABEL: buildvec_v2bf16:
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; RV64-ZFBFMIN: # %bb.0:
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; RV64-ZFBFMIN-NEXT: fmv.x.h a0, fa1
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; RV64-ZFBFMIN-NEXT: fmv.x.h a1, fa0
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; RV64-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; RV64-ZFBFMIN-NEXT: vmv.v.x v8, a1
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; RV64-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0
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; RV64-ZFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: buildvec_v2bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
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; ZVFBFA-NEXT: vfmv.v.f v8, fa0
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; ZVFBFA-NEXT: vfslide1down.vf v8, v8, fa1
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; ZVFBFA-NEXT: ret
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%v1 = insertelement <2 x bfloat> poison, bfloat %a, i64 0
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%v2 = insertelement <2 x bfloat> %v1, bfloat %b, i64 1
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ret <2 x bfloat> %v2
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}
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define <2 x bfloat> @vid_v2bf16() {
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; CHECK-LABEL: vid_v2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 260096
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; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v8, a0
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; CHECK-NEXT: ret
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;
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; ZVFBFA-LABEL: vid_v2bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFBFA-NEXT: vid.v v8
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; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
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; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
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; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
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; ZVFBFA-NEXT: ret
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ret <2 x bfloat> <bfloat 0.0, bfloat 1.0>
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}
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define <2 x bfloat> @vid_addend1_v2bf16() {
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; CHECK-LABEL: vid_addend1_v2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: lui a0, 4
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; CHECK-NEXT: vsll.vi v8, v8, 7
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; CHECK-NEXT: addi a0, a0, -128
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; CHECK-NEXT: vadd.vx v8, v8, a0
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; CHECK-NEXT: ret
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;
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; ZVFBFA-LABEL: vid_addend1_v2bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFBFA-NEXT: vid.v v8
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; ZVFBFA-NEXT: vadd.vi v8, v8, 1
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; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
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; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
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; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
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; ZVFBFA-NEXT: ret
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ret <2 x bfloat> <bfloat 1.0, bfloat 2.0>
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}
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define <2 x bfloat> @vid_denominator2_v2bf16() {
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; CHECK-LABEL: vid_denominator2_v2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: lui a0, 4
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; CHECK-NEXT: vsll.vi v8, v8, 7
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; CHECK-NEXT: addi a0, a0, -256
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; CHECK-NEXT: vadd.vx v8, v8, a0
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; CHECK-NEXT: ret
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;
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; ZVFBFA-LABEL: vid_denominator2_v2bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: lui a0, %hi(.LCPI4_0)
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; ZVFBFA-NEXT: addi a0, a0, %lo(.LCPI4_0)
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; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFBFA-NEXT: vle16.v v8, (a0)
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; ZVFBFA-NEXT: ret
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ret <2 x bfloat> <bfloat 0.5, bfloat 1.0>
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}
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define <2 x bfloat> @vid_step2_v2bf16() {
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; CHECK-LABEL: vid_step2_v2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsll.vi v8, v8, 14
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; CHECK-NEXT: ret
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;
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; ZVFBFA-LABEL: vid_step2_v2bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFBFA-NEXT: vid.v v8
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; ZVFBFA-NEXT: vadd.vv v8, v8, v8
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; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
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; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
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; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
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; ZVFBFA-NEXT: ret
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ret <2 x bfloat> <bfloat 0.0, bfloat 2.0>
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; RV32: {{.*}}
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; RV32ZVFBFMIN: {{.*}}
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; RV64: {{.*}}
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; RV64ZVFBFMIN: {{.*}}
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