derek.holloway
7502bf64a4
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908 lines
30 KiB
LLVM
908 lines
30 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH,ZVFH32
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH,ZVFH64
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN,ZVFHMIN32
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN,ZVFHMIN64
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32,ZVFBFA
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64,ZVFBFA
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define void @fp2si_v2f32_v2i32(ptr %x, ptr %y) {
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; CHECK-LABEL: fp2si_v2f32_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
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; CHECK-NEXT: vse32.v v8, (a1)
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; CHECK-NEXT: ret
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%a = load <2 x float>, ptr %x
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%d = fptosi <2 x float> %a to <2 x i32>
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store <2 x i32> %d, ptr %y
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ret void
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}
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define void @fp2ui_v2f32_v2i32(ptr %x, ptr %y) {
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; CHECK-LABEL: fp2ui_v2f32_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
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; CHECK-NEXT: vse32.v v8, (a1)
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; CHECK-NEXT: ret
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%a = load <2 x float>, ptr %x
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%d = fptoui <2 x float> %a to <2 x i32>
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store <2 x i32> %d, ptr %y
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ret void
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}
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define <2 x i1> @fp2si_v2f32_v2i1(<2 x float> %x) {
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; CHECK-LABEL: fp2si_v2f32_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
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; CHECK-NEXT: vmsne.vi v0, v9, 0
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; CHECK-NEXT: ret
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%z = fptosi <2 x float> %x to <2 x i1>
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ret <2 x i1> %z
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}
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define <2 x i15> @fp2si_v2f32_v2i15(<2 x float> %x) {
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; CHECK-LABEL: fp2si_v2f32_v2i15:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%z = fptosi <2 x float> %x to <2 x i15>
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ret <2 x i15> %z
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}
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define <2 x i15> @fp2ui_v2f32_v2i15(<2 x float> %x) {
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; CHECK-LABEL: fp2ui_v2f32_v2i15:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%z = fptoui <2 x float> %x to <2 x i15>
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ret <2 x i15> %z
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}
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define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) {
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; CHECK-LABEL: fp2ui_v2f32_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
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; CHECK-NEXT: vmsne.vi v0, v9, 0
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; CHECK-NEXT: ret
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%z = fptoui <2 x float> %x to <2 x i1>
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ret <2 x i1> %z
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}
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define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
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; CHECK-LABEL: fp2si_v3f32_v3i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
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; CHECK-NEXT: vse32.v v8, (a1)
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; CHECK-NEXT: ret
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%a = load <3 x float>, ptr %x
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%d = fptosi <3 x float> %a to <3 x i32>
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store <3 x i32> %d, ptr %y
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ret void
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}
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define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
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; CHECK-LABEL: fp2ui_v3f32_v3i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
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; CHECK-NEXT: vse32.v v8, (a1)
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; CHECK-NEXT: ret
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%a = load <3 x float>, ptr %x
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%d = fptoui <3 x float> %a to <3 x i32>
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store <3 x i32> %d, ptr %y
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ret void
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}
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define <3 x i1> @fp2si_v3f32_v3i1(<3 x float> %x) {
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; CHECK-LABEL: fp2si_v3f32_v3i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
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; CHECK-NEXT: vmsne.vi v0, v9, 0
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; CHECK-NEXT: ret
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%z = fptosi <3 x float> %x to <3 x i1>
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ret <3 x i1> %z
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}
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; FIXME: This is expanded when they could be widened + promoted
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define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
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; ZVFH32-LABEL: fp2si_v3f32_v3i15:
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; ZVFH32: # %bb.0:
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; ZVFH32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH32-NEXT: vfncvt.rtz.x.f.w v9, v8
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; ZVFH32-NEXT: vslidedown.vi v8, v9, 2
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; ZVFH32-NEXT: vmv.x.s a1, v9
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; ZVFH32-NEXT: vslidedown.vi v9, v9, 1
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; ZVFH32-NEXT: vmv.x.s a2, v8
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; ZVFH32-NEXT: slli a1, a1, 17
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; ZVFH32-NEXT: srli a1, a1, 17
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; ZVFH32-NEXT: slli a3, a2, 30
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; ZVFH32-NEXT: or a1, a1, a3
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; ZVFH32-NEXT: vmv.x.s a3, v9
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; ZVFH32-NEXT: slli a2, a2, 17
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; ZVFH32-NEXT: slli a3, a3, 17
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; ZVFH32-NEXT: srli a2, a2, 19
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; ZVFH32-NEXT: srli a3, a3, 2
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; ZVFH32-NEXT: or a1, a1, a3
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; ZVFH32-NEXT: sw a1, 0(a0)
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; ZVFH32-NEXT: sh a2, 4(a0)
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; ZVFH32-NEXT: ret
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;
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; ZVFH64-LABEL: fp2si_v3f32_v3i15:
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; ZVFH64: # %bb.0:
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; ZVFH64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH64-NEXT: vfncvt.rtz.x.f.w v9, v8
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; ZVFH64-NEXT: vmv.x.s a1, v9
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; ZVFH64-NEXT: vslidedown.vi v8, v9, 1
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; ZVFH64-NEXT: vslidedown.vi v9, v9, 2
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; ZVFH64-NEXT: slli a1, a1, 49
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; ZVFH64-NEXT: vmv.x.s a2, v8
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; ZVFH64-NEXT: vmv.x.s a3, v9
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; ZVFH64-NEXT: srli a1, a1, 49
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; ZVFH64-NEXT: slli a2, a2, 49
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; ZVFH64-NEXT: slli a3, a3, 30
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; ZVFH64-NEXT: srli a2, a2, 34
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; ZVFH64-NEXT: or a1, a1, a3
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; ZVFH64-NEXT: or a1, a1, a2
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; ZVFH64-NEXT: slli a2, a1, 19
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; ZVFH64-NEXT: srli a2, a2, 51
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; ZVFH64-NEXT: sw a1, 0(a0)
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; ZVFH64-NEXT: sh a2, 4(a0)
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; ZVFH64-NEXT: ret
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;
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; ZVFHMIN32-LABEL: fp2si_v3f32_v3i15:
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; ZVFHMIN32: # %bb.0:
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; ZVFHMIN32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN32-NEXT: vfncvt.rtz.x.f.w v9, v8
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; ZVFHMIN32-NEXT: vslidedown.vi v8, v9, 2
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; ZVFHMIN32-NEXT: vmv.x.s a1, v9
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; ZVFHMIN32-NEXT: vslidedown.vi v9, v9, 1
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; ZVFHMIN32-NEXT: vmv.x.s a2, v8
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; ZVFHMIN32-NEXT: slli a1, a1, 17
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; ZVFHMIN32-NEXT: srli a1, a1, 17
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; ZVFHMIN32-NEXT: slli a3, a2, 30
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; ZVFHMIN32-NEXT: or a1, a1, a3
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; ZVFHMIN32-NEXT: vmv.x.s a3, v9
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; ZVFHMIN32-NEXT: slli a2, a2, 17
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; ZVFHMIN32-NEXT: slli a3, a3, 17
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; ZVFHMIN32-NEXT: srli a2, a2, 19
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; ZVFHMIN32-NEXT: srli a3, a3, 2
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; ZVFHMIN32-NEXT: or a1, a1, a3
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; ZVFHMIN32-NEXT: sw a1, 0(a0)
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; ZVFHMIN32-NEXT: sh a2, 4(a0)
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; ZVFHMIN32-NEXT: ret
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;
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; ZVFHMIN64-LABEL: fp2si_v3f32_v3i15:
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; ZVFHMIN64: # %bb.0:
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; ZVFHMIN64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN64-NEXT: vfncvt.rtz.x.f.w v9, v8
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; ZVFHMIN64-NEXT: vmv.x.s a1, v9
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; ZVFHMIN64-NEXT: vslidedown.vi v8, v9, 1
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; ZVFHMIN64-NEXT: vslidedown.vi v9, v9, 2
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; ZVFHMIN64-NEXT: slli a1, a1, 49
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; ZVFHMIN64-NEXT: vmv.x.s a2, v8
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; ZVFHMIN64-NEXT: vmv.x.s a3, v9
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; ZVFHMIN64-NEXT: srli a1, a1, 49
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; ZVFHMIN64-NEXT: slli a2, a2, 49
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; ZVFHMIN64-NEXT: slli a3, a3, 30
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; ZVFHMIN64-NEXT: srli a2, a2, 34
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; ZVFHMIN64-NEXT: or a1, a1, a3
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; ZVFHMIN64-NEXT: or a1, a1, a2
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; ZVFHMIN64-NEXT: slli a2, a1, 19
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; ZVFHMIN64-NEXT: srli a2, a2, 51
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; ZVFHMIN64-NEXT: sw a1, 0(a0)
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; ZVFHMIN64-NEXT: sh a2, 4(a0)
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; ZVFHMIN64-NEXT: ret
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%z = fptosi <3 x float> %x to <3 x i15>
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ret <3 x i15> %z
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}
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; FIXME: This is expanded when they could be widened + promoted
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define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
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; ZVFH32-LABEL: fp2ui_v3f32_v3i15:
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; ZVFH32: # %bb.0:
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; ZVFH32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH32-NEXT: vfncvt.rtz.x.f.w v9, v8
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; ZVFH32-NEXT: vslidedown.vi v8, v9, 2
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; ZVFH32-NEXT: vmv.x.s a1, v9
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; ZVFH32-NEXT: vslidedown.vi v9, v9, 1
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; ZVFH32-NEXT: vmv.x.s a2, v8
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; ZVFH32-NEXT: slli a1, a1, 16
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; ZVFH32-NEXT: srli a1, a1, 16
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; ZVFH32-NEXT: slli a3, a2, 30
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; ZVFH32-NEXT: or a1, a1, a3
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; ZVFH32-NEXT: vmv.x.s a3, v9
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; ZVFH32-NEXT: slli a2, a2, 17
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; ZVFH32-NEXT: slli a3, a3, 16
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; ZVFH32-NEXT: srli a2, a2, 19
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; ZVFH32-NEXT: srli a3, a3, 1
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; ZVFH32-NEXT: or a1, a1, a3
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; ZVFH32-NEXT: sw a1, 0(a0)
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; ZVFH32-NEXT: sh a2, 4(a0)
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; ZVFH32-NEXT: ret
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;
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; ZVFH64-LABEL: fp2ui_v3f32_v3i15:
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; ZVFH64: # %bb.0:
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; ZVFH64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH64-NEXT: vfncvt.rtz.x.f.w v9, v8
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; ZVFH64-NEXT: vmv.x.s a1, v9
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; ZVFH64-NEXT: vslidedown.vi v8, v9, 1
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; ZVFH64-NEXT: vslidedown.vi v9, v9, 2
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; ZVFH64-NEXT: slli a1, a1, 48
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; ZVFH64-NEXT: vmv.x.s a2, v8
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; ZVFH64-NEXT: vmv.x.s a3, v9
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; ZVFH64-NEXT: srli a1, a1, 48
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; ZVFH64-NEXT: slli a2, a2, 48
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; ZVFH64-NEXT: slli a3, a3, 30
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; ZVFH64-NEXT: srli a2, a2, 33
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; ZVFH64-NEXT: or a1, a1, a3
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; ZVFH64-NEXT: or a1, a1, a2
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; ZVFH64-NEXT: slli a2, a1, 19
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; ZVFH64-NEXT: srli a2, a2, 51
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; ZVFH64-NEXT: sw a1, 0(a0)
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; ZVFH64-NEXT: sh a2, 4(a0)
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; ZVFH64-NEXT: ret
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;
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; ZVFHMIN32-LABEL: fp2ui_v3f32_v3i15:
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; ZVFHMIN32: # %bb.0:
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; ZVFHMIN32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN32-NEXT: vfncvt.rtz.x.f.w v9, v8
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; ZVFHMIN32-NEXT: vslidedown.vi v8, v9, 2
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; ZVFHMIN32-NEXT: vmv.x.s a1, v9
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; ZVFHMIN32-NEXT: vslidedown.vi v9, v9, 1
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; ZVFHMIN32-NEXT: vmv.x.s a2, v8
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; ZVFHMIN32-NEXT: slli a1, a1, 16
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; ZVFHMIN32-NEXT: srli a1, a1, 16
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; ZVFHMIN32-NEXT: slli a3, a2, 30
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; ZVFHMIN32-NEXT: or a1, a1, a3
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; ZVFHMIN32-NEXT: vmv.x.s a3, v9
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; ZVFHMIN32-NEXT: slli a2, a2, 17
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; ZVFHMIN32-NEXT: slli a3, a3, 16
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; ZVFHMIN32-NEXT: srli a2, a2, 19
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; ZVFHMIN32-NEXT: srli a3, a3, 1
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; ZVFHMIN32-NEXT: or a1, a1, a3
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; ZVFHMIN32-NEXT: sw a1, 0(a0)
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; ZVFHMIN32-NEXT: sh a2, 4(a0)
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; ZVFHMIN32-NEXT: ret
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;
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; ZVFHMIN64-LABEL: fp2ui_v3f32_v3i15:
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; ZVFHMIN64: # %bb.0:
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; ZVFHMIN64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN64-NEXT: vfncvt.rtz.x.f.w v9, v8
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; ZVFHMIN64-NEXT: vmv.x.s a1, v9
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; ZVFHMIN64-NEXT: vslidedown.vi v8, v9, 1
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; ZVFHMIN64-NEXT: vslidedown.vi v9, v9, 2
|
|
; ZVFHMIN64-NEXT: slli a1, a1, 48
|
|
; ZVFHMIN64-NEXT: vmv.x.s a2, v8
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v9
|
|
; ZVFHMIN64-NEXT: srli a1, a1, 48
|
|
; ZVFHMIN64-NEXT: slli a2, a2, 48
|
|
; ZVFHMIN64-NEXT: slli a3, a3, 30
|
|
; ZVFHMIN64-NEXT: srli a2, a2, 33
|
|
; ZVFHMIN64-NEXT: or a1, a1, a3
|
|
; ZVFHMIN64-NEXT: or a1, a1, a2
|
|
; ZVFHMIN64-NEXT: slli a2, a1, 19
|
|
; ZVFHMIN64-NEXT: srli a2, a2, 51
|
|
; ZVFHMIN64-NEXT: sw a1, 0(a0)
|
|
; ZVFHMIN64-NEXT: sh a2, 4(a0)
|
|
; ZVFHMIN64-NEXT: ret
|
|
%z = fptoui <3 x float> %x to <3 x i15>
|
|
ret <3 x i15> %z
|
|
}
|
|
|
|
define <3 x i1> @fp2ui_v3f32_v3i1(<3 x float> %x) {
|
|
; CHECK-LABEL: fp2ui_v3f32_v3i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
|
|
; CHECK-NEXT: vmsne.vi v0, v9, 0
|
|
; CHECK-NEXT: ret
|
|
%z = fptoui <3 x float> %x to <3 x i1>
|
|
ret <3 x i1> %z
|
|
}
|
|
|
|
define void @fp2si_v8f32_v8i32(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2si_v8f32_v8i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
|
|
; CHECK-NEXT: vse32.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x float>, ptr %x
|
|
%d = fptosi <8 x float> %a to <8 x i32>
|
|
store <8 x i32> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v8f32_v8i32(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2ui_v8f32_v8i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
|
|
; CHECK-NEXT: vse32.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x float>, ptr %x
|
|
%d = fptoui <8 x float> %a to <8 x i32>
|
|
store <8 x i32> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define <8 x i1> @fp2si_v8f32_v8i1(<8 x float> %x) {
|
|
; CHECK-LABEL: fp2si_v8f32_v8i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
|
|
; CHECK-NEXT: vmsne.vi v0, v10, 0
|
|
; CHECK-NEXT: ret
|
|
%z = fptosi <8 x float> %x to <8 x i1>
|
|
ret <8 x i1> %z
|
|
}
|
|
|
|
define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) {
|
|
; CHECK-LABEL: fp2ui_v8f32_v8i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
|
|
; CHECK-NEXT: vmsne.vi v0, v10, 0
|
|
; CHECK-NEXT: ret
|
|
%z = fptoui <8 x float> %x to <8 x i1>
|
|
ret <8 x i1> %z
|
|
}
|
|
|
|
define void @fp2si_v2f32_v2i64(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2si_v2f32_v2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
|
|
; CHECK-NEXT: vse64.v v9, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <2 x float>, ptr %x
|
|
%d = fptosi <2 x float> %a to <2 x i64>
|
|
store <2 x i64> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v2f32_v2i64(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2ui_v2f32_v2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
|
|
; CHECK-NEXT: vse64.v v9, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <2 x float>, ptr %x
|
|
%d = fptoui <2 x float> %a to <2 x i64>
|
|
store <2 x i64> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2si_v8f32_v8i64(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2si_v8f32_v8i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v12, (a0)
|
|
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12
|
|
; CHECK-NEXT: vse64.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x float>, ptr %x
|
|
%d = fptosi <8 x float> %a to <8 x i64>
|
|
store <8 x i64> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2ui_v8f32_v8i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v12, (a0)
|
|
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12
|
|
; CHECK-NEXT: vse64.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x float>, ptr %x
|
|
%d = fptoui <8 x float> %a to <8 x i64>
|
|
store <8 x i64> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2si_v2bf16_v2i64(ptr %x, ptr %y) {
|
|
; ZVFBFMIN-LABEL: fp2si_v2bf16_v2i64:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvt.rtz.x.f.v v8, v9
|
|
; ZVFBFMIN-NEXT: vse64.v v8, (a1)
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: fp2si_v2bf16_v2i64:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
|
|
; ZVFBFA-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFBFA-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFBFA-NEXT: vfwcvt.rtz.x.f.v v8, v9
|
|
; ZVFBFA-NEXT: vse64.v v8, (a1)
|
|
; ZVFBFA-NEXT: ret
|
|
%a = load <2 x bfloat>, ptr %x
|
|
%d = fptosi <2 x bfloat> %a to <2 x i64>
|
|
store <2 x i64> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v2bf16_v2i64(ptr %x, ptr %y) {
|
|
; ZVFBFMIN-LABEL: fp2ui_v2bf16_v2i64:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v9
|
|
; ZVFBFMIN-NEXT: vse64.v v8, (a1)
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: fp2ui_v2bf16_v2i64:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
|
|
; ZVFBFA-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFBFA-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFBFA-NEXT: vfwcvt.rtz.xu.f.v v8, v9
|
|
; ZVFBFA-NEXT: vse64.v v8, (a1)
|
|
; ZVFBFA-NEXT: ret
|
|
%a = load <2 x bfloat>, ptr %x
|
|
%d = fptoui <2 x bfloat> %a to <2 x i64>
|
|
store <2 x i64> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define <2 x i1> @fp2si_v2bf16_v2i1(<2 x bfloat> %x) {
|
|
; ZVFBFMIN-LABEL: fp2si_v2bf16_v2i1:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
|
|
; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
|
|
; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: fp2si_v2bf16_v2i1:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
|
|
; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
|
|
; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
|
|
; ZVFBFA-NEXT: ret
|
|
%z = fptosi <2 x bfloat> %x to <2 x i1>
|
|
ret <2 x i1> %z
|
|
}
|
|
|
|
define <2 x i1> @fp2ui_v2bf16_v2i1(<2 x bfloat> %x) {
|
|
; ZVFBFMIN-LABEL: fp2ui_v2bf16_v2i1:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
|
|
; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
|
|
; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: fp2ui_v2bf16_v2i1:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
|
|
; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
|
|
; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
|
|
; ZVFBFA-NEXT: ret
|
|
%z = fptoui <2 x bfloat> %x to <2 x i1>
|
|
ret <2 x i1> %z
|
|
}
|
|
|
|
define void @fp2si_v64bf16_v64i16(ptr %x, ptr %y) {
|
|
; ZVFBFMIN-LABEL: fp2si_v64bf16_v64i16:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: li a2, 64
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFBFMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFMIN-NEXT: li a0, 32
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFBFMIN-NEXT: vslidedown.vx v24, v8, a0
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v16
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
|
|
; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v24, v16
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFBFMIN-NEXT: vslideup.vx v8, v24, a0
|
|
; ZVFBFMIN-NEXT: vse16.v v8, (a1)
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: fp2si_v64bf16_v64i16:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: li a2, 64
|
|
; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFBFA-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFA-NEXT: li a0, 32
|
|
; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
|
|
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
|
|
; ZVFBFA-NEXT: vslidedown.vx v24, v8, a0
|
|
; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v8, v16
|
|
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
|
|
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v24, v16
|
|
; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFBFA-NEXT: vslideup.vx v8, v24, a0
|
|
; ZVFBFA-NEXT: vse16.v v8, (a1)
|
|
; ZVFBFA-NEXT: ret
|
|
%a = load <64 x bfloat>, ptr %x
|
|
%d = fptosi <64 x bfloat> %a to <64 x i16>
|
|
store <64 x i16> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v64bf16_v64i16(ptr %x, ptr %y) {
|
|
; ZVFBFMIN-LABEL: fp2ui_v64bf16_v64i16:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: li a2, 64
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFBFMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFMIN-NEXT: li a0, 32
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFBFMIN-NEXT: vslidedown.vx v24, v8, a0
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
|
|
; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v24, v16
|
|
; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFBFMIN-NEXT: vslideup.vx v8, v24, a0
|
|
; ZVFBFMIN-NEXT: vse16.v v8, (a1)
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: fp2ui_v64bf16_v64i16:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: li a2, 64
|
|
; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFBFA-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFA-NEXT: li a0, 32
|
|
; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
|
|
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
|
|
; ZVFBFA-NEXT: vslidedown.vx v24, v8, a0
|
|
; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v8, v16
|
|
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
|
|
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v24, v16
|
|
; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFBFA-NEXT: vslideup.vx v8, v24, a0
|
|
; ZVFBFA-NEXT: vse16.v v8, (a1)
|
|
; ZVFBFA-NEXT: ret
|
|
%a = load <64 x bfloat>, ptr %x
|
|
%d = fptoui <64 x bfloat> %a to <64 x i16>
|
|
store <64 x i16> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2si_v2bf16_v2i8(ptr %x, ptr %y) {
|
|
; ZVFBFMIN-LABEL: fp2si_v2bf16_v2i8:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
|
|
; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
|
|
; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
|
|
; ZVFBFMIN-NEXT: vse8.v v8, (a1)
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: fp2si_v2bf16_v2i8:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
|
|
; ZVFBFA-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
|
|
; ZVFBFA-NEXT: vse8.v v9, (a1)
|
|
; ZVFBFA-NEXT: ret
|
|
%a = load <2 x bfloat>, ptr %x
|
|
%d = fptosi <2 x bfloat> %a to <2 x i8>
|
|
store <2 x i8> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v2bf16_v2i8(ptr %x, ptr %y) {
|
|
; ZVFBFMIN-LABEL: fp2ui_v2bf16_v2i8:
|
|
; ZVFBFMIN: # %bb.0:
|
|
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFBFMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
|
|
; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
|
|
; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
|
|
; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
|
|
; ZVFBFMIN-NEXT: vse8.v v8, (a1)
|
|
; ZVFBFMIN-NEXT: ret
|
|
;
|
|
; ZVFBFA-LABEL: fp2ui_v2bf16_v2i8:
|
|
; ZVFBFA: # %bb.0:
|
|
; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
|
|
; ZVFBFA-NEXT: vle16.v v8, (a0)
|
|
; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
|
|
; ZVFBFA-NEXT: vse8.v v9, (a1)
|
|
; ZVFBFA-NEXT: ret
|
|
%a = load <2 x bfloat>, ptr %x
|
|
%d = fptoui <2 x bfloat> %a to <2 x i8>
|
|
store <2 x i8> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2si_v2f16_v2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
|
|
; CHECK-NEXT: vse64.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <2 x half>, ptr %x
|
|
%d = fptosi <2 x half> %a to <2 x i64>
|
|
store <2 x i64> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v2f16_v2i64(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2ui_v2f16_v2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
|
|
; CHECK-NEXT: vse64.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <2 x half>, ptr %x
|
|
%d = fptoui <2 x half> %a to <2 x i64>
|
|
store <2 x i64> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) {
|
|
; ZVFH-LABEL: fp2si_v2f16_v2i1:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
|
|
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
|
|
; ZVFH-NEXT: vmsne.vi v0, v9, 0
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: fp2si_v2f16_v2i1:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
|
|
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%z = fptosi <2 x half> %x to <2 x i1>
|
|
ret <2 x i1> %z
|
|
}
|
|
|
|
define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) {
|
|
; ZVFH-LABEL: fp2ui_v2f16_v2i1:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
|
|
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
|
|
; ZVFH-NEXT: vmsne.vi v0, v9, 0
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: fp2ui_v2f16_v2i1:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
|
|
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%z = fptoui <2 x half> %x to <2 x i1>
|
|
ret <2 x i1> %z
|
|
}
|
|
|
|
define void @fp2si_v64f16_v64i16(ptr %x, ptr %y) {
|
|
; ZVFH-LABEL: fp2si_v64f16_v64i16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a2, 64
|
|
; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
|
|
; ZVFH-NEXT: vse16.v v8, (a1)
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: fp2si_v64f16_v64i16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v24, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v16
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v24, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslideup.vx v8, v24, a0
|
|
; ZVFHMIN-NEXT: vse16.v v8, (a1)
|
|
; ZVFHMIN-NEXT: ret
|
|
%a = load <64 x half>, ptr %x
|
|
%d = fptosi <64 x half> %a to <64 x i16>
|
|
store <64 x i16> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v64f16_v64i16(ptr %x, ptr %y) {
|
|
; ZVFH-LABEL: fp2ui_v64f16_v64i16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a2, 64
|
|
; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8
|
|
; ZVFH-NEXT: vse16.v v8, (a1)
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: fp2ui_v64f16_v64i16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v24, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v24, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslideup.vx v8, v24, a0
|
|
; ZVFHMIN-NEXT: vse16.v v8, (a1)
|
|
; ZVFHMIN-NEXT: ret
|
|
%a = load <64 x half>, ptr %x
|
|
%d = fptoui <64 x half> %a to <64 x i16>
|
|
store <64 x i16> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2si_v2f64_v2i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vnsrl.wi v8, v9, 0
|
|
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
|
|
; CHECK-NEXT: vnsrl.wi v8, v8, 0
|
|
; CHECK-NEXT: vse8.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <2 x double>, ptr %x
|
|
%d = fptosi <2 x double> %a to <2 x i8>
|
|
store <2 x i8> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v2f64_v2i8(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2ui_v2f64_v2i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vnsrl.wi v8, v9, 0
|
|
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
|
|
; CHECK-NEXT: vnsrl.wi v8, v8, 0
|
|
; CHECK-NEXT: vse8.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <2 x double>, ptr %x
|
|
%d = fptoui <2 x double> %a to <2 x i8>
|
|
store <2 x i8> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define <2 x i1> @fp2si_v2f64_v2i1(<2 x double> %x) {
|
|
; CHECK-LABEL: fp2si_v2f64_v2i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
|
|
; CHECK-NEXT: vmsne.vi v0, v9, 0
|
|
; CHECK-NEXT: ret
|
|
%z = fptosi <2 x double> %x to <2 x i1>
|
|
ret <2 x i1> %z
|
|
}
|
|
|
|
define <2 x i1> @fp2ui_v2f64_v2i1(<2 x double> %x) {
|
|
; CHECK-LABEL: fp2ui_v2f64_v2i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
|
|
; CHECK-NEXT: vmsne.vi v0, v9, 0
|
|
; CHECK-NEXT: ret
|
|
%z = fptoui <2 x double> %x to <2 x i1>
|
|
ret <2 x i1> %z
|
|
}
|
|
|
|
define void @fp2si_v8f64_v8i8(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2si_v8f64_v8i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vnsrl.wi v8, v12, 0
|
|
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vnsrl.wi v8, v8, 0
|
|
; CHECK-NEXT: vse8.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x double>, ptr %x
|
|
%d = fptosi <8 x double> %a to <8 x i8>
|
|
store <8 x i8> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define void @fp2ui_v8f64_v8i8(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: fp2ui_v8f64_v8i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vnsrl.wi v8, v12, 0
|
|
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vnsrl.wi v8, v8, 0
|
|
; CHECK-NEXT: vse8.v v8, (a1)
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x double>, ptr %x
|
|
%d = fptoui <8 x double> %a to <8 x i8>
|
|
store <8 x i8> %d, ptr %y
|
|
ret void
|
|
}
|
|
|
|
define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) {
|
|
; CHECK-LABEL: fp2si_v8f64_v8i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
|
|
; CHECK-NEXT: vmsne.vi v0, v12, 0
|
|
; CHECK-NEXT: ret
|
|
%z = fptosi <8 x double> %x to <8 x i1>
|
|
ret <8 x i1> %z
|
|
}
|
|
|
|
define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) {
|
|
; CHECK-LABEL: fp2ui_v8f64_v8i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
|
|
; CHECK-NEXT: vmsne.vi v0, v12, 0
|
|
; CHECK-NEXT: ret
|
|
%z = fptoui <8 x double> %x to <8 x i1>
|
|
ret <8 x i1> %z
|
|
}
|