derek.holloway
7502bf64a4
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6463 lines
228 KiB
LLVM
6463 lines
228 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFH,RV32 %s
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFH,RV64 %s
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFHMIN,RV32,ZVFHMIN32 %s
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; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFHMIN,RV64,ZVFHMIN64 %s
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define half @vreduce_fadd_v1f16(<1 x half> %v, half %s) {
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; ZVFH-LABEL: vreduce_fadd_v1f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.f.s fa5, v8
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; ZVFH-NEXT: fadd.h fa0, fa0, fa5
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_fadd_v1f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vmv.x.s a0, v8
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; ZVFHMIN-NEXT: fmv.h.x fa5, a0
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; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
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; ZVFHMIN-NEXT: ret
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%red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v1f16(<1 x half> %v, half %s) {
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; ZVFH-LABEL: vreduce_ord_fadd_v1f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vfredosum.vs v8, v8, v9
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; ZVFH-NEXT: vfmv.f.s fa0, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_ord_fadd_v1f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vmv.x.s a0, v8
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; ZVFHMIN-NEXT: fmv.h.x fa5, a0
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; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
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; ZVFHMIN-NEXT: ret
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%red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
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ret half %red
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}
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define half @vreduce_fadd_v2f16(ptr %x, half %s) {
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; ZVFH-LABEL: vreduce_fadd_v2f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFH-NEXT: vle16.v v8, (a0)
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vfredusum.vs v8, v8, v9
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; ZVFH-NEXT: vfmv.f.s fa0, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_fadd_v2f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; ZVFHMIN-NEXT: vle16.v v8, (a0)
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; ZVFHMIN-NEXT: lui a0, 524288
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; ZVFHMIN-NEXT: vmv.s.x v9, a0
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; ZVFHMIN-NEXT: vfredusum.vs v8, v10, v9
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
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; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
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; ZVFHMIN-NEXT: ret
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%v = load <2 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v2f16(ptr %x, half %s) {
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; ZVFH-LABEL: vreduce_ord_fadd_v2f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFH-NEXT: vle16.v v8, (a0)
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vfredosum.vs v8, v8, v9
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; ZVFH-NEXT: vfmv.f.s fa0, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_ord_fadd_v2f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vle16.v v8, (a0)
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; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 1
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; ZVFHMIN-NEXT: vmv.x.s a0, v8
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; ZVFHMIN-NEXT: fmv.h.x fa5, a0
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; ZVFHMIN-NEXT: vmv.x.s a0, v9
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; ZVFHMIN-NEXT: fmv.h.x fa4, a0
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; ZVFHMIN-NEXT: fadd.h fa5, fa0, fa5
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; ZVFHMIN-NEXT: fadd.h fa0, fa5, fa4
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; ZVFHMIN-NEXT: ret
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%v = load <2 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
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ret half %red
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}
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define half @vreduce_fadd_v4f16(ptr %x, half %s) {
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; ZVFH-LABEL: vreduce_fadd_v4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH-NEXT: vle16.v v8, (a0)
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vfredusum.vs v8, v8, v9
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; ZVFH-NEXT: vfmv.f.s fa0, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_fadd_v4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vle16.v v8, (a0)
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; ZVFHMIN-NEXT: lui a0, 524288
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; ZVFHMIN-NEXT: vmv.s.x v9, a0
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vfredusum.vs v8, v10, v9
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
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; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
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; ZVFHMIN-NEXT: ret
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%v = load <4 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v4f16(ptr %x, half %s) {
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; ZVFH-LABEL: vreduce_ord_fadd_v4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH-NEXT: vle16.v v8, (a0)
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vfredosum.vs v8, v8, v9
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; ZVFH-NEXT: vfmv.f.s fa0, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_ord_fadd_v4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vle16.v v8, (a0)
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; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
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; ZVFHMIN-NEXT: vmv.x.s a0, v8
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; ZVFHMIN-NEXT: fmv.h.x fa5, a0
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; ZVFHMIN-NEXT: vmv.x.s a0, v9
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; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
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; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
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; ZVFHMIN-NEXT: fmv.h.x fa4, a0
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; ZVFHMIN-NEXT: vmv.x.s a0, v9
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; ZVFHMIN-NEXT: fmv.h.x fa3, a0
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; ZVFHMIN-NEXT: vmv.x.s a0, v8
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; ZVFHMIN-NEXT: fmv.h.x fa2, a0
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; ZVFHMIN-NEXT: fadd.h fa5, fa0, fa5
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; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
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; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
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; ZVFHMIN-NEXT: fadd.h fa0, fa5, fa4
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; ZVFHMIN-NEXT: ret
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%v = load <4 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
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ret half %red
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}
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define half @vreduce_fadd_v7f16(ptr %x, half %s) {
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; ZVFH-LABEL: vreduce_fadd_v7f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 7, e16, m1, ta, ma
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; ZVFH-NEXT: vle16.v v8, (a0)
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vfredusum.vs v8, v8, v9
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; ZVFH-NEXT: vfmv.f.s fa0, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_fadd_v7f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vle16.v v10, (a0)
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; ZVFHMIN-NEXT: lui a0, 1048568
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; ZVFHMIN-NEXT: vmv.s.x v8, a0
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; ZVFHMIN-NEXT: lui a0, 524288
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; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vslideup.vi v10, v8, 7
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vmv.s.x v10, a0
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; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v10
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
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; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
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; ZVFHMIN-NEXT: ret
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%v = load <7 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v7f16(half %s, <7 x half> %v)
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ret half %red
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}
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define half @vreduce_fadd_v8f16(ptr %x, half %s) {
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; ZVFH-LABEL: vreduce_fadd_v8f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; ZVFH-NEXT: vle16.v v8, (a0)
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vfredusum.vs v8, v8, v9
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; ZVFH-NEXT: vfmv.f.s fa0, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_fadd_v8f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vle16.v v10, (a0)
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; ZVFHMIN-NEXT: lui a0, 524288
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; ZVFHMIN-NEXT: vmv.s.x v11, a0
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v11
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
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; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
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; ZVFHMIN-NEXT: ret
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%v = load <8 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v8f16(ptr %x, half %s) {
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; ZVFH-LABEL: vreduce_ord_fadd_v8f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; ZVFH-NEXT: vle16.v v8, (a0)
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vfredosum.vs v8, v8, v9
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; ZVFH-NEXT: vfmv.f.s fa0, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vreduce_ord_fadd_v8f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vle16.v v8, (a0)
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; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 7
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; ZVFHMIN-NEXT: vmv.x.s a0, v8
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; ZVFHMIN-NEXT: fmv.h.x fa5, a0
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; ZVFHMIN-NEXT: vmv.x.s a0, v9
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; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 6
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; ZVFHMIN-NEXT: fmv.h.x fa4, a0
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; ZVFHMIN-NEXT: vmv.x.s a0, v9
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; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 5
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; ZVFHMIN-NEXT: fmv.h.x fa3, a0
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; ZVFHMIN-NEXT: vmv.x.s a0, v9
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; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 4
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; ZVFHMIN-NEXT: fmv.h.x fa2, a0
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; ZVFHMIN-NEXT: vmv.x.s a0, v9
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|
; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
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|
; ZVFHMIN-NEXT: fmv.h.x fa1, a0
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|
; ZVFHMIN-NEXT: vmv.x.s a0, v9
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|
; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
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|
; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
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; ZVFHMIN-NEXT: fmv.h.x ft0, a0
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|
; ZVFHMIN-NEXT: vmv.x.s a0, v9
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|
; ZVFHMIN-NEXT: fmv.h.x ft1, a0
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|
; ZVFHMIN-NEXT: vmv.x.s a0, v8
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|
; ZVFHMIN-NEXT: fmv.h.x ft2, a0
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|
; ZVFHMIN-NEXT: fadd.h fa5, fa0, fa5
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|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft2
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|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft1
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|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft0
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|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa1
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
|
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; ZVFHMIN-NEXT: fadd.h fa0, fa5, fa4
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|
; ZVFHMIN-NEXT: ret
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%v = load <8 x half>, ptr %x
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|
%red = call half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
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|
ret half %red
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|
}
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|
define half @vreduce_fadd_v16f16(ptr %x, half %s) {
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|
; ZVFH-LABEL: vreduce_fadd_v16f16:
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|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
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|
; ZVFH-NEXT: vfmv.s.f v10, fa0
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|
; ZVFH-NEXT: vfredusum.vs v8, v8, v10
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
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|
; ZVFH-NEXT: ret
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|
;
|
|
; ZVFHMIN-LABEL: vreduce_fadd_v16f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v12, (a0)
|
|
; ZVFHMIN-NEXT: lui a0, 524288
|
|
; ZVFHMIN-NEXT: vmv.s.x v14, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v14
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <16 x half>, ptr %x
|
|
%red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_ord_fadd_v16f16(ptr %x, half %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fadd_v16f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v10, fa0
|
|
; ZVFH-NEXT: vfredosum.vs v8, v8, v10
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_ord_fadd_v16f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 15
|
|
; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 14
|
|
; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 13
|
|
; ZVFHMIN-NEXT: vmv.x.s a0, v10
|
|
; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 12
|
|
; ZVFHMIN-NEXT: vmv.x.s a1, v12
|
|
; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 11
|
|
; ZVFHMIN-NEXT: vmv.x.s a2, v14
|
|
; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 10
|
|
; ZVFHMIN-NEXT: vmv.x.s a3, v10
|
|
; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 9
|
|
; ZVFHMIN-NEXT: vmv.x.s a4, v12
|
|
; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 8
|
|
; ZVFHMIN-NEXT: vmv.x.s a5, v14
|
|
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 7
|
|
; ZVFHMIN-NEXT: vslidedown.vi v11, v8, 6
|
|
; ZVFHMIN-NEXT: vmv.x.s a6, v10
|
|
; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 5
|
|
; ZVFHMIN-NEXT: vslidedown.vi v13, v8, 4
|
|
; ZVFHMIN-NEXT: vmv.x.s a7, v12
|
|
; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 3
|
|
; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 2
|
|
; ZVFHMIN-NEXT: vmv.x.s t0, v8
|
|
; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
|
|
; ZVFHMIN-NEXT: vmv.x.s t1, v9
|
|
; ZVFHMIN-NEXT: vmv.x.s t2, v11
|
|
; ZVFHMIN-NEXT: vmv.x.s t3, v10
|
|
; ZVFHMIN-NEXT: fmv.h.x fa5, t0
|
|
; ZVFHMIN-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN-NEXT: fmv.h.x fa3, a1
|
|
; ZVFHMIN-NEXT: fmv.h.x fa2, a2
|
|
; ZVFHMIN-NEXT: fmv.h.x fa1, a3
|
|
; ZVFHMIN-NEXT: fmv.h.x ft0, a4
|
|
; ZVFHMIN-NEXT: fmv.h.x ft1, a5
|
|
; ZVFHMIN-NEXT: fmv.h.x ft2, a6
|
|
; ZVFHMIN-NEXT: fmv.h.x ft3, a7
|
|
; ZVFHMIN-NEXT: fmv.h.x ft4, t1
|
|
; ZVFHMIN-NEXT: fmv.h.x ft5, t2
|
|
; ZVFHMIN-NEXT: fmv.h.x ft6, t3
|
|
; ZVFHMIN-NEXT: vmv.x.s a0, v13
|
|
; ZVFHMIN-NEXT: fmv.h.x ft7, a0
|
|
; ZVFHMIN-NEXT: vmv.x.s a0, v12
|
|
; ZVFHMIN-NEXT: fmv.h.x fa6, a0
|
|
; ZVFHMIN-NEXT: vmv.x.s a0, v14
|
|
; ZVFHMIN-NEXT: fmv.h.x fa7, a0
|
|
; ZVFHMIN-NEXT: vmv.x.s a0, v8
|
|
; ZVFHMIN-NEXT: fmv.h.x ft8, a0
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa0, fa5
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft8
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa7
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa6
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft7
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft6
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft5
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft4
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft3
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft2
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft1
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft0
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa1
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
|
|
; ZVFHMIN-NEXT: fadd.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <16 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fadd_v32f16(ptr %x, half %s) {
|
|
; ZVFH-LABEL: vreduce_fadd_v32f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 32
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v12, fa0
|
|
; ZVFH-NEXT: vfredusum.vs v8, v8, v12
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fadd_v32f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v16, (a0)
|
|
; ZVFHMIN-NEXT: lui a0, 524288
|
|
; ZVFHMIN-NEXT: vmv.s.x v20, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v20
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <32 x half>, ptr %x
|
|
%red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_ord_fadd_v32f16(ptr %x, half %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fadd_v32f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 32
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v12, fa0
|
|
; ZVFH-NEXT: vfredosum.vs v8, v8, v12
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN32-LABEL: vreduce_ord_fadd_v32f16:
|
|
; ZVFHMIN32: # %bb.0:
|
|
; ZVFHMIN32-NEXT: addi sp, sp, -128
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 128
|
|
; ZVFHMIN32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
|
|
; ZVFHMIN32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
|
|
; ZVFHMIN32-NEXT: .cfi_offset ra, -4
|
|
; ZVFHMIN32-NEXT: .cfi_offset s0, -8
|
|
; ZVFHMIN32-NEXT: addi s0, sp, 128
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
|
|
; ZVFHMIN32-NEXT: andi sp, sp, -64
|
|
; ZVFHMIN32-NEXT: li a1, 32
|
|
; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
|
|
; ZVFHMIN32-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN32-NEXT: mv a0, sp
|
|
; ZVFHMIN32-NEXT: vse16.v v8, (a0)
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 15
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 14
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 13
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 12
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 11
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 2
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 1
|
|
; ZVFHMIN32-NEXT: vmv.x.s a5, v8
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
|
|
; ZVFHMIN32-NEXT: vmv.x.s a0, v16
|
|
; ZVFHMIN32-NEXT: vmv.x.s a1, v18
|
|
; ZVFHMIN32-NEXT: vmv.x.s a2, v20
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v22
|
|
; ZVFHMIN32-NEXT: vmv.x.s a4, v8
|
|
; ZVFHMIN32-NEXT: vmv.x.s a6, v11
|
|
; ZVFHMIN32-NEXT: vmv.x.s a7, v13
|
|
; ZVFHMIN32-NEXT: vmv.x.s t0, v15
|
|
; ZVFHMIN32-NEXT: vmv.x.s t1, v17
|
|
; ZVFHMIN32-NEXT: vmv.x.s t2, v19
|
|
; ZVFHMIN32-NEXT: vmv.x.s t3, v21
|
|
; ZVFHMIN32-NEXT: vmv.x.s t4, v23
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa5, a5
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa0, fa5
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, t4
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, t3
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, t2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, t1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, t0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a7
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a6
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a4
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v14
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v12
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v10
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: lh a0, 32(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 34(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 36(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 38(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 40(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 42(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 44(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 46(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 48(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 50(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 52(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 54(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 56(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 58(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 60(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 62(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: fadd.h fa0, fa5, fa4
|
|
; ZVFHMIN32-NEXT: addi sp, s0, -128
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 128
|
|
; ZVFHMIN32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
|
|
; ZVFHMIN32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
|
|
; ZVFHMIN32-NEXT: .cfi_restore ra
|
|
; ZVFHMIN32-NEXT: .cfi_restore s0
|
|
; ZVFHMIN32-NEXT: addi sp, sp, 128
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN32-NEXT: ret
|
|
;
|
|
; ZVFHMIN64-LABEL: vreduce_ord_fadd_v32f16:
|
|
; ZVFHMIN64: # %bb.0:
|
|
; ZVFHMIN64-NEXT: addi sp, sp, -128
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 128
|
|
; ZVFHMIN64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
|
|
; ZVFHMIN64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
|
|
; ZVFHMIN64-NEXT: .cfi_offset ra, -8
|
|
; ZVFHMIN64-NEXT: .cfi_offset s0, -16
|
|
; ZVFHMIN64-NEXT: addi s0, sp, 128
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
|
|
; ZVFHMIN64-NEXT: andi sp, sp, -64
|
|
; ZVFHMIN64-NEXT: li a1, 32
|
|
; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
|
|
; ZVFHMIN64-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN64-NEXT: mv a0, sp
|
|
; ZVFHMIN64-NEXT: vse16.v v8, (a0)
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 15
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 14
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 13
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 12
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 11
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 2
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 1
|
|
; ZVFHMIN64-NEXT: vmv.x.s a5, v8
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v16
|
|
; ZVFHMIN64-NEXT: vmv.x.s a1, v18
|
|
; ZVFHMIN64-NEXT: vmv.x.s a2, v20
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v22
|
|
; ZVFHMIN64-NEXT: vmv.x.s a4, v8
|
|
; ZVFHMIN64-NEXT: vmv.x.s a6, v11
|
|
; ZVFHMIN64-NEXT: vmv.x.s a7, v13
|
|
; ZVFHMIN64-NEXT: vmv.x.s t0, v15
|
|
; ZVFHMIN64-NEXT: vmv.x.s t1, v17
|
|
; ZVFHMIN64-NEXT: vmv.x.s t2, v19
|
|
; ZVFHMIN64-NEXT: vmv.x.s t3, v21
|
|
; ZVFHMIN64-NEXT: vmv.x.s t4, v23
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa5, a5
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa0, fa5
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, t4
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, t3
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, t2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, t1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, t0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a7
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a6
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a4
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v14
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v12
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v10
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: lh a0, 32(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 34(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 36(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 38(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 40(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 42(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 44(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 46(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 48(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 50(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 52(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 54(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 56(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 58(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 60(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 62(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: fadd.h fa0, fa5, fa4
|
|
; ZVFHMIN64-NEXT: addi sp, s0, -128
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 128
|
|
; ZVFHMIN64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
|
|
; ZVFHMIN64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
|
|
; ZVFHMIN64-NEXT: .cfi_restore ra
|
|
; ZVFHMIN64-NEXT: .cfi_restore s0
|
|
; ZVFHMIN64-NEXT: addi sp, sp, 128
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN64-NEXT: ret
|
|
%v = load <32 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fadd_v64f16(ptr %x, half %s) {
|
|
; ZVFH-LABEL: vreduce_fadd_v64f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v16, fa0
|
|
; ZVFH-NEXT: vfredusum.vs v8, v8, v16
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fadd_v64f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: lui a1, 524288
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vmv.s.x v24, a1
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredusum.vs v12, v16, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v12
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v16, v24
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_ord_fadd_v64f16(ptr %x, half %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fadd_v64f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v16, fa0
|
|
; ZVFH-NEXT: vfredosum.vs v8, v8, v16
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN32-LABEL: vreduce_ord_fadd_v64f16:
|
|
; ZVFHMIN32: # %bb.0:
|
|
; ZVFHMIN32-NEXT: addi sp, sp, -256
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 256
|
|
; ZVFHMIN32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill
|
|
; ZVFHMIN32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
|
|
; ZVFHMIN32-NEXT: .cfi_offset ra, -4
|
|
; ZVFHMIN32-NEXT: .cfi_offset s0, -8
|
|
; ZVFHMIN32-NEXT: addi s0, sp, 256
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
|
|
; ZVFHMIN32-NEXT: andi sp, sp, -128
|
|
; ZVFHMIN32-NEXT: li a1, 64
|
|
; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN32-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN32-NEXT: mv a0, sp
|
|
; ZVFHMIN32-NEXT: vse16.v v8, (a0)
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 15
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 14
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 13
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 12
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 11
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 9
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 2
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 1
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v8
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
|
|
; ZVFHMIN32-NEXT: vmv.x.s a0, v18
|
|
; ZVFHMIN32-NEXT: vmv.x.s a1, v20
|
|
; ZVFHMIN32-NEXT: vmv.x.s a2, v22
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa5, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v23
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa0, fa5
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v21
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v19
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v17
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v15
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v13
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v11
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v8
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v16
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v14
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v12
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v10
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: lh a0, 32(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 34(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 36(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 38(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 40(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 42(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 44(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 46(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 48(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 50(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 52(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 54(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 56(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 58(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 60(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 62(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 64(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 66(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 68(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 70(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 72(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 74(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 76(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 78(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 80(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 82(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 84(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 86(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 88(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 90(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 92(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 94(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 96(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 98(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 100(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 102(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 104(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 106(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 108(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 110(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 112(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 114(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 116(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 118(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 120(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 122(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 124(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 126(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: fadd.h fa0, fa5, fa4
|
|
; ZVFHMIN32-NEXT: addi sp, s0, -256
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 256
|
|
; ZVFHMIN32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload
|
|
; ZVFHMIN32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload
|
|
; ZVFHMIN32-NEXT: .cfi_restore ra
|
|
; ZVFHMIN32-NEXT: .cfi_restore s0
|
|
; ZVFHMIN32-NEXT: addi sp, sp, 256
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN32-NEXT: ret
|
|
;
|
|
; ZVFHMIN64-LABEL: vreduce_ord_fadd_v64f16:
|
|
; ZVFHMIN64: # %bb.0:
|
|
; ZVFHMIN64-NEXT: addi sp, sp, -256
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 256
|
|
; ZVFHMIN64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
|
|
; ZVFHMIN64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
|
|
; ZVFHMIN64-NEXT: .cfi_offset ra, -8
|
|
; ZVFHMIN64-NEXT: .cfi_offset s0, -16
|
|
; ZVFHMIN64-NEXT: addi s0, sp, 256
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
|
|
; ZVFHMIN64-NEXT: andi sp, sp, -128
|
|
; ZVFHMIN64-NEXT: li a1, 64
|
|
; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN64-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN64-NEXT: mv a0, sp
|
|
; ZVFHMIN64-NEXT: vse16.v v8, (a0)
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 15
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 14
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 13
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 12
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 11
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 9
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 2
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 1
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v8
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v18
|
|
; ZVFHMIN64-NEXT: vmv.x.s a1, v20
|
|
; ZVFHMIN64-NEXT: vmv.x.s a2, v22
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa5, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v23
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa0, fa5
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v21
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v19
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v17
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v15
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v13
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v11
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v8
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v16
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v14
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v12
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v10
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: lh a0, 32(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 34(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 36(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 38(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 40(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 42(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 44(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 46(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 48(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 50(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 52(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 54(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 56(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 58(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 60(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 62(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 64(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 66(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 68(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 70(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 72(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 74(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 76(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 78(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 80(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 82(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 84(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 86(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 88(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 90(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 92(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 94(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 96(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 98(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 100(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 102(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 104(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 106(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 108(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 110(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 112(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 114(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 116(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 118(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 120(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 122(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 124(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 126(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: fadd.h fa0, fa5, fa4
|
|
; ZVFHMIN64-NEXT: addi sp, s0, -256
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 256
|
|
; ZVFHMIN64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
|
|
; ZVFHMIN64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
|
|
; ZVFHMIN64-NEXT: .cfi_restore ra
|
|
; ZVFHMIN64-NEXT: .cfi_restore s0
|
|
; ZVFHMIN64-NEXT: addi sp, sp, 256
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN64-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fadd_v128f16(ptr %x, half %s) {
|
|
; ZVFH-LABEL: vreduce_fadd_v128f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: addi a0, a0, 128
|
|
; ZVFH-NEXT: vle16.v v16, (a0)
|
|
; ZVFH-NEXT: vfadd.vv v8, v8, v16
|
|
; ZVFH-NEXT: vfmv.s.f v16, fa0
|
|
; ZVFH-NEXT: vfredusum.vs v8, v8, v16
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fadd_v128f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: addi sp, sp, -16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a2, a1, 2
|
|
; ZVFHMIN-NEXT: add a1, a2, a1
|
|
; ZVFHMIN-NEXT: sub sp, sp, a1
|
|
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x05, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 5 * vlenb
|
|
; ZVFHMIN-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v16, (a0)
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a1)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: lui a1, 524288
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfadd.vv v24, v24, v0
|
|
; ZVFHMIN-NEXT: vmv.s.x v7, a1
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 2
|
|
; ZVFHMIN-NEXT: add a1, sp, a1
|
|
; ZVFHMIN-NEXT: addi a1, a1, 16
|
|
; ZVFHMIN-NEXT: vs1r.v v7, (a1) # vscale x 8-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a0
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfadd.vv v8, v0, v16
|
|
; ZVFHMIN-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v8
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 2
|
|
; ZVFHMIN-NEXT: add a0, sp, a0
|
|
; ZVFHMIN-NEXT: addi a0, a0, 16
|
|
; ZVFHMIN-NEXT: vl1r.v v28, (a0) # vscale x 8-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredusum.vs v16, v16, v28
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v16
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v28
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a0, 2
|
|
; ZVFHMIN-NEXT: add a0, a1, a0
|
|
; ZVFHMIN-NEXT: add sp, sp, a0
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
|
|
; ZVFHMIN-NEXT: addi sp, sp, 16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_ord_fadd_v128f16(ptr %x, half %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fadd_v128f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: addi a1, a0, 128
|
|
; ZVFH-NEXT: li a2, 64
|
|
; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vle16.v v16, (a1)
|
|
; ZVFH-NEXT: vfmv.s.f v24, fa0
|
|
; ZVFH-NEXT: vfredosum.vs v8, v8, v24
|
|
; ZVFH-NEXT: vfredosum.vs v8, v16, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN32-LABEL: vreduce_ord_fadd_v128f16:
|
|
; ZVFHMIN32: # %bb.0:
|
|
; ZVFHMIN32-NEXT: addi sp, sp, -384
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 384
|
|
; ZVFHMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
|
|
; ZVFHMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
|
|
; ZVFHMIN32-NEXT: .cfi_offset ra, -4
|
|
; ZVFHMIN32-NEXT: .cfi_offset s0, -8
|
|
; ZVFHMIN32-NEXT: addi s0, sp, 384
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
|
|
; ZVFHMIN32-NEXT: andi sp, sp, -128
|
|
; ZVFHMIN32-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN32-NEXT: li a2, 64
|
|
; ZVFHMIN32-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN32-NEXT: vle16.v v8, (a1)
|
|
; ZVFHMIN32-NEXT: mv a1, sp
|
|
; ZVFHMIN32-NEXT: vse16.v v8, (a1)
|
|
; ZVFHMIN32-NEXT: vle16.v v16, (a0)
|
|
; ZVFHMIN32-NEXT: addi a0, sp, 128
|
|
; ZVFHMIN32-NEXT: vse16.v v16, (a0)
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 15
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v12, v16, 14
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v26, v16, 13
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v14, v16, 12
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v18, v16, 11
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v15, v16, 7
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v19, v16, 6
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v27, v16, 5
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v30, v16, 4
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v31, v16, 3
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v28, v16, 2
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v16
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v29, v16, 1
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v20, v16, 10
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v22, v16, 9
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v24, v16, 8
|
|
; ZVFHMIN32-NEXT: vmv.x.s a0, v10
|
|
; ZVFHMIN32-NEXT: vmv.x.s a1, v12
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 15
|
|
; ZVFHMIN32-NEXT: vmv.x.s a2, v26
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 14
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa5, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v29
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa0, fa5
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v28
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v28, v8, 13
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v31
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v30
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 12
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v27
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v19
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v26, v8, 11
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v15
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v24
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v24, v8, 10
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v22
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
|
|
; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v20
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v18
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 3
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: vmv.x.s a3, v14
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 2
|
|
; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: lh a0, 160(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 162(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 164(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 166(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 168(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 170(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 172(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 174(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 176(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 178(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 180(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 182(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 184(sp)
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; ZVFHMIN32-NEXT: lh a1, 186(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 188(sp)
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; ZVFHMIN32-NEXT: lh a3, 190(sp)
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 192(sp)
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; ZVFHMIN32-NEXT: lh a1, 194(sp)
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; ZVFHMIN32-NEXT: lh a2, 196(sp)
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; ZVFHMIN32-NEXT: lh a3, 198(sp)
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 200(sp)
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; ZVFHMIN32-NEXT: lh a1, 202(sp)
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; ZVFHMIN32-NEXT: lh a2, 204(sp)
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; ZVFHMIN32-NEXT: lh a3, 206(sp)
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 208(sp)
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; ZVFHMIN32-NEXT: lh a1, 210(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 212(sp)
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; ZVFHMIN32-NEXT: lh a3, 214(sp)
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 216(sp)
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; ZVFHMIN32-NEXT: lh a1, 218(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 220(sp)
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; ZVFHMIN32-NEXT: lh a3, 222(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 224(sp)
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; ZVFHMIN32-NEXT: lh a1, 226(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 228(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 230(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 232(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 234(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 236(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 238(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 240(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 242(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 244(sp)
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; ZVFHMIN32-NEXT: lh a3, 246(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 248(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 250(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 252(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 254(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v8
|
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; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
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; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: vmv.x.s a1, v12
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: vmv.x.s a2, v10
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: vmv.x.s a3, v28
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v19
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v14
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v18
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v17
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v15
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v13
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v11
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v8
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v22
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v24
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v26
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: vmv.x.s a0, v16
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: lh a0, 32(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 34(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 36(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 38(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 40(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 42(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 44(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 46(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 48(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 50(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 52(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 54(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 56(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 58(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 60(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 62(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 64(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 66(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 68(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 70(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 72(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 74(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 76(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 78(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 80(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 82(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 84(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 86(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 88(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 90(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 92(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 94(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 96(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 98(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 100(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 102(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 104(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 106(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 108(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 110(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
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; ZVFHMIN32-NEXT: lh a0, 112(sp)
|
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; ZVFHMIN32-NEXT: lh a1, 114(sp)
|
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; ZVFHMIN32-NEXT: lh a2, 116(sp)
|
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; ZVFHMIN32-NEXT: lh a3, 118(sp)
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
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; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
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; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: lh a0, 120(sp)
|
|
; ZVFHMIN32-NEXT: lh a1, 122(sp)
|
|
; ZVFHMIN32-NEXT: lh a2, 124(sp)
|
|
; ZVFHMIN32-NEXT: lh a3, 126(sp)
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN32-NEXT: fadd.h fa0, fa5, fa4
|
|
; ZVFHMIN32-NEXT: addi sp, s0, -384
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 384
|
|
; ZVFHMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
|
|
; ZVFHMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
|
|
; ZVFHMIN32-NEXT: .cfi_restore ra
|
|
; ZVFHMIN32-NEXT: .cfi_restore s0
|
|
; ZVFHMIN32-NEXT: addi sp, sp, 384
|
|
; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN32-NEXT: ret
|
|
;
|
|
; ZVFHMIN64-LABEL: vreduce_ord_fadd_v128f16:
|
|
; ZVFHMIN64: # %bb.0:
|
|
; ZVFHMIN64-NEXT: addi sp, sp, -384
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 384
|
|
; ZVFHMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
|
|
; ZVFHMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
|
|
; ZVFHMIN64-NEXT: .cfi_offset ra, -8
|
|
; ZVFHMIN64-NEXT: .cfi_offset s0, -16
|
|
; ZVFHMIN64-NEXT: addi s0, sp, 384
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
|
|
; ZVFHMIN64-NEXT: andi sp, sp, -128
|
|
; ZVFHMIN64-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN64-NEXT: li a2, 64
|
|
; ZVFHMIN64-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN64-NEXT: vle16.v v8, (a1)
|
|
; ZVFHMIN64-NEXT: mv a1, sp
|
|
; ZVFHMIN64-NEXT: vse16.v v8, (a1)
|
|
; ZVFHMIN64-NEXT: vle16.v v16, (a0)
|
|
; ZVFHMIN64-NEXT: addi a0, sp, 128
|
|
; ZVFHMIN64-NEXT: vse16.v v16, (a0)
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 15
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v12, v16, 14
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v26, v16, 13
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v14, v16, 12
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v18, v16, 11
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v15, v16, 7
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v19, v16, 6
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v27, v16, 5
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v30, v16, 4
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v31, v16, 3
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v28, v16, 2
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v16
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v29, v16, 1
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v20, v16, 10
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v22, v16, 9
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v24, v16, 8
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v10
|
|
; ZVFHMIN64-NEXT: vmv.x.s a1, v12
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 15
|
|
; ZVFHMIN64-NEXT: vmv.x.s a2, v26
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 14
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa5, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v29
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa0, fa5
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v28
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v28, v8, 13
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v31
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v30
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 12
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v27
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v19
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v26, v8, 11
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v15
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v24
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v24, v8, 10
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v22
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v20
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v18
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 3
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v14
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 2
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: lh a0, 160(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 162(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 164(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 166(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 168(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 170(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 172(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 174(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 176(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 178(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 180(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 182(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 184(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 186(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 188(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 190(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 192(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 194(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 196(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 198(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 200(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 202(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 204(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 206(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 208(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 210(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 212(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 214(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 216(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 218(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 220(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 222(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 224(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 226(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 228(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 230(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 232(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 234(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 236(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 238(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 240(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 242(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 244(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 246(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 248(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 250(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 252(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 254(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v8
|
|
; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
|
|
; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: vmv.x.s a1, v12
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: vmv.x.s a2, v10
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: vmv.x.s a3, v28
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v19
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v14
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v18
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v17
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v15
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v13
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v11
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v8
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v22
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v24
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v26
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: vmv.x.s a0, v16
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: lh a0, 32(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 34(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 36(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 38(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 40(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 42(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 44(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 46(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 48(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 50(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 52(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 54(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 56(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 58(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 60(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 62(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 64(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 66(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 68(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 70(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 72(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 74(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 76(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 78(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 80(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 82(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 84(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 86(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 88(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 90(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 92(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 94(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 96(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 98(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 100(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 102(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 104(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 106(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 108(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 110(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 112(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 114(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 116(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 118(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: lh a0, 120(sp)
|
|
; ZVFHMIN64-NEXT: lh a1, 122(sp)
|
|
; ZVFHMIN64-NEXT: lh a2, 124(sp)
|
|
; ZVFHMIN64-NEXT: lh a3, 126(sp)
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
|
|
; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
|
|
; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
|
|
; ZVFHMIN64-NEXT: fadd.h fa0, fa5, fa4
|
|
; ZVFHMIN64-NEXT: addi sp, s0, -384
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 384
|
|
; ZVFHMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
|
|
; ZVFHMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
|
|
; ZVFHMIN64-NEXT: .cfi_restore ra
|
|
; ZVFHMIN64-NEXT: .cfi_restore s0
|
|
; ZVFHMIN64-NEXT: addi sp, sp, 384
|
|
; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN64-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v1f32(<1 x float> %v, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v1f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa5, v8
|
|
; CHECK-NEXT: fadd.s fa0, fa0, fa5
|
|
; CHECK-NEXT: ret
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v1f32(<1 x float> %v, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v1f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v1f32(<1 x half> %v, float %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v1f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa5, v9
|
|
; CHECK-NEXT: fadd.s fa0, fa0, fa5
|
|
; CHECK-NEXT: ret
|
|
%e = fpext <1 x half> %v to <1 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v1f32(<1 x half> %v, float %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fwadd_v1f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 1, e32, m1, ta, ma
|
|
; ZVFH-NEXT: vfmv.s.f v9, fa0
|
|
; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vfwredosum.vs v8, v8, v9
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_ord_fwadd_v1f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
|
|
; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%e = fpext <1 x half> %v to <1 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v2f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v2f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v2f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_fwadd_v2f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v9, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vfwredusum.vs v8, v8, v9
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fwadd_v2f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <2 x half>, ptr %x
|
|
%e = fpext <2 x half> %v to <2 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v2f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fwadd_v2f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v9, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vfwredosum.vs v8, v8, v9
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_ord_fwadd_v2f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
|
|
; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <2 x half>, ptr %x
|
|
%e = fpext <2 x half> %v to <2 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v4f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v4f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v4f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_fwadd_v4f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v9, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vfwredusum.vs v8, v8, v9
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fwadd_v4f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%e = fpext <4 x half> %v to <4 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v4f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fwadd_v4f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v9, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vfwredosum.vs v8, v8, v9
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_ord_fwadd_v4f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
|
|
; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%e = fpext <4 x half> %v to <4 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v7f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v7f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v7f32(float %s, <7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v7f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v7f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v7f32(float %s, <7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v7f32_neutralstart(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: lui a0, 524288
|
|
; CHECK-NEXT: vmv.s.x v10, a0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v7f32_neutralstart_nsz(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart_nsz:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: lui a0, 524288
|
|
; CHECK-NEXT: vmv.s.x v10, a0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call nsz float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v7f32_neutralstart_fast(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart_fast:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmv.s.x v10, zero
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call fast float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v8f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v8f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v8f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_fwadd_v8f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v9, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFH-NEXT: vfwredusum.vs v8, v8, v9
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fwadd_v8f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v10, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v10, fa0
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v10
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <8 x half>, ptr %x
|
|
%e = fpext <8 x half> %v to <8 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v8f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fwadd_v8f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v9, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFH-NEXT: vfwredosum.vs v8, v8, v9
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_ord_fwadd_v8f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v10, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v10, fa0
|
|
; ZVFHMIN-NEXT: vfredosum.vs v8, v8, v10
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <8 x half>, ptr %x
|
|
%e = fpext <8 x half> %v to <8 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v16f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v16f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v16f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_fwadd_v16f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v10, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFH-NEXT: vfwredusum.vs v8, v8, v10
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fwadd_v16f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v12, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v12, fa0
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v12
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <16 x half>, ptr %x
|
|
%e = fpext <16 x half> %v to <16 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v16f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fwadd_v16f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v10, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFH-NEXT: vfwredosum.vs v8, v8, v10
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_ord_fwadd_v16f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v12, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v12, fa0
|
|
; ZVFHMIN-NEXT: vfredosum.vs v8, v8, v12
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <16 x half>, ptr %x
|
|
%e = fpext <16 x half> %v to <16 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v32f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v32f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v32f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v32f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v32f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_fwadd_v32f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 32
|
|
; ZVFH-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v12, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vfwredusum.vs v8, v8, v12
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fwadd_v32f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v16, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v16, fa0
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v16
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <32 x half>, ptr %x
|
|
%e = fpext <32 x half> %v to <32 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v32f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fwadd_v32f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 32
|
|
; ZVFH-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfmv.s.f v12, fa0
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vfwredosum.vs v8, v8, v12
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_ord_fwadd_v32f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v16, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v16, fa0
|
|
; ZVFHMIN-NEXT: vfredosum.vs v8, v8, v16
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <32 x half>, ptr %x
|
|
%e = fpext <32 x half> %v to <32 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fadd_v64f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v64f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: vfadd.vv v8, v8, v16
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v64f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v64f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi a1, a0, 128
|
|
; CHECK-NEXT: li a2, 32
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vle32.v v16, (a1)
|
|
; CHECK-NEXT: vfmv.s.f v24, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v24
|
|
; CHECK-NEXT: vfredosum.vs v8, v16, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v64f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_fwadd_v64f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: li a0, 32
|
|
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vslidedown.vx v16, v8, a0
|
|
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vfwadd.vv v24, v8, v16
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFH-NEXT: vfmv.s.f v8, fa0
|
|
; ZVFH-NEXT: vfredusum.vs v8, v24, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fwadd_v64f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfadd.vv v8, v16, v24
|
|
; ZVFHMIN-NEXT: vfmv.s.f v16, fa0
|
|
; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v16
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%e = fpext <64 x half> %v to <64 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) {
|
|
; ZVFH-LABEL: vreduce_ord_fwadd_v64f32:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: li a0, 32
|
|
; ZVFH-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
|
; ZVFH-NEXT: vfmv.s.f v24, fa0
|
|
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vslidedown.vx v16, v8, a0
|
|
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vfwredosum.vs v8, v8, v24
|
|
; ZVFH-NEXT: vfwredosum.vs v8, v16, v8
|
|
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_ord_fwadd_v64f32:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.s.f v7, fa0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v16, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredosum.vs v16, v24, v7
|
|
; ZVFHMIN-NEXT: vfredosum.vs v8, v8, v16
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%e = fpext <64 x half> %v to <64 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define double @vreduce_fadd_v1f64(<1 x double> %v, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v1f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa5, v8
|
|
; CHECK-NEXT: fadd.d fa0, fa0, fa5
|
|
; CHECK-NEXT: ret
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v1f64(<1 x double> %v, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v1f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v1f64(<1 x float> %v, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v1f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa5, v9
|
|
; CHECK-NEXT: fadd.d fa0, fa0, fa5
|
|
; CHECK-NEXT: ret
|
|
%e = fpext <1 x float> %v to <1 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v1f64(<1 x float> %v, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v1f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%e = fpext <1 x float> %v to <1 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fadd_v2f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v2f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v2f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%e = fpext <2 x float> %v to <2 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v2f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%e = fpext <2 x float> %v to <2 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fadd_v4f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v4f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v4f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%e = fpext <4 x float> %v to <4 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v4f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%e = fpext <4 x float> %v to <4 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fadd_v8f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v8f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v8f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%e = fpext <8 x float> %v to <8 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v8f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%e = fpext <8 x float> %v to <8 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fadd_v16f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v16f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v16f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v12
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%e = fpext <16 x float> %v to <16 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v16f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%e = fpext <16 x float> %v to <16 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fadd_v32f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v16, (a0)
|
|
; CHECK-NEXT: vfadd.vv v8, v8, v16
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v32f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi a1, a0, 128
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vle64.v v16, (a1)
|
|
; CHECK-NEXT: vfmv.s.f v24, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v24
|
|
; CHECK-NEXT: vfredosum.vs v8, v16, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v32f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
|
|
; CHECK-NEXT: vslidedown.vi v16, v8, 16
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfwadd.vv v24, v8, v16
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v8, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v24, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%e = fpext <32 x float> %v to <32 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v24, fa0
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
|
|
; CHECK-NEXT: vslidedown.vi v16, v8, 16
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v24
|
|
; CHECK-NEXT: vfwredosum.vs v8, v16, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%e = fpext <32 x float> %v to <32 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define half @vreduce_fmin_v2f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmin_v2f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmin_v2f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v9, v9
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <2 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmin_v4f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmin_v4f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmin_v4f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v9, v9
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmin_v4f16_nonans(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmin_v4f16_nonans:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmin_v4f16_nonans:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v9, v9
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmin_v4f16_nonans_noinfs(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmin_v4f16_nonans_noinfs:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmin_v4f16_nonans_noinfs:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v9, v9
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmin_v64f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmin_v64f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmin_v64f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmin.vs v12, v16, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v12
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v16, v16
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fmin.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmin.v64f16(<64 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmin_v128f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmin_v128f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: addi a0, a0, 128
|
|
; ZVFH-NEXT: vle16.v v16, (a0)
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v16
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmin_v128f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: addi sp, sp, -16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 2
|
|
; ZVFHMIN-NEXT: sub sp, sp, a1
|
|
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
|
|
; ZVFHMIN-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v24, (a0)
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a1)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a0
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmin.vv v16, v16, v0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmin.vv v8, v0, v24
|
|
; ZVFHMIN-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmin.vs v16, v16, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v16
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fmin.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 2
|
|
; ZVFHMIN-NEXT: add sp, sp, a0
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
|
|
; ZVFHMIN-NEXT: addi sp, sp, 16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define float @vreduce_fmin_v2f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmin_v4f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmin_v4f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmin_v4f32_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f32_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmin_v7f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v7f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: vmv.s.x v10, a0
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmin.v7f32(<7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmin_v128f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v128f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: addi a2, a0, 384
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a2)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v24, (a0)
|
|
; CHECK-NEXT: vle32.v v0, (a1)
|
|
; CHECK-NEXT: vfmin.vv v8, v24, v8
|
|
; CHECK-NEXT: vfmin.vv v16, v16, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v16, v8
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define double @vreduce_fmin_v2f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmin_v4f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmin_v4f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmin_v4f64_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f64_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmin_v32f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v16, (a0)
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define half @vreduce_fmax_v2f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmax_v2f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmax_v2f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v9, v9
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <2 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmax_v4f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmax_v4f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmax_v4f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v9, v9
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmax_v4f16_nonans(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmax_v4f16_nonans:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmax_v4f16_nonans:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v9, v9
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmax_v4f16_nonans_noinfs(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmax_v4f16_nonans_noinfs:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmax_v4f16_nonans_noinfs:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v9, v9
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmax_v64f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmax_v64f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmax_v64f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmax.vs v12, v16, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v12
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v16, v16
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fmax.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmax.v64f16(<64 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmax_v128f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmax_v128f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: addi a0, a0, 128
|
|
; ZVFH-NEXT: vle16.v v16, (a0)
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v16
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmax_v128f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: addi sp, sp, -16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 2
|
|
; ZVFHMIN-NEXT: sub sp, sp, a1
|
|
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
|
|
; ZVFHMIN-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v24, (a0)
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a1)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a0
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmax.vv v8, v0, v24
|
|
; ZVFHMIN-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmax.vs v16, v16, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v16
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fmax.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 2
|
|
; ZVFHMIN-NEXT: add sp, sp, a0
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
|
|
; ZVFHMIN-NEXT: addi sp, sp, 16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define float @vreduce_fmax_v2f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmax_v4f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmax_v4f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmax_v4f32_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f32_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmax_v7f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v7f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: lui a0, 1047552
|
|
; CHECK-NEXT: vmv.s.x v10, a0
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmax.v7f32(<7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmax_v128f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v128f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: addi a2, a0, 384
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a2)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v24, (a0)
|
|
; CHECK-NEXT: vle32.v v0, (a1)
|
|
; CHECK-NEXT: vfmax.vv v8, v24, v8
|
|
; CHECK-NEXT: vfmax.vv v16, v16, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v16, v8
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define double @vreduce_fmax_v2f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmax_v4f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmax_v4f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmax_v4f64_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f64_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmax_v32f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v16, (a0)
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define float @vreduce_nsz_fadd_v4f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_nsz_fadd_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define half @vreduce_fminimum_v64f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fminimum_v64f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vmfne.vv v16, v8, v8
|
|
; ZVFH-NEXT: vcpop.m a0, v16
|
|
; ZVFH-NEXT: beqz a0, .LBB109_2
|
|
; ZVFH-NEXT: # %bb.1:
|
|
; ZVFH-NEXT: lui a0, 8
|
|
; ZVFH-NEXT: addi a0, a0, -512
|
|
; ZVFH-NEXT: fmv.h.x fa0, a0
|
|
; ZVFH-NEXT: ret
|
|
; ZVFH-NEXT: .LBB109_2:
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fminimum_v64f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v24, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfne.vv v12, v16, v16
|
|
; ZVFHMIN-NEXT: vcpop.m a0, v12
|
|
; ZVFHMIN-NEXT: lui a1, 523264
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
|
|
; ZVFHMIN-NEXT: beqz a0, .LBB109_2
|
|
; ZVFHMIN-NEXT: # %bb.1:
|
|
; ZVFHMIN-NEXT: fmv.s fa4, fa5
|
|
; ZVFHMIN-NEXT: j .LBB109_3
|
|
; ZVFHMIN-NEXT: .LBB109_2:
|
|
; ZVFHMIN-NEXT: vfredmin.vs v12, v16, v16
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v12
|
|
; ZVFHMIN-NEXT: .LBB109_3:
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfne.vv v8, v16, v16
|
|
; ZVFHMIN-NEXT: vcpop.m a0, v8
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB109_5
|
|
; ZVFHMIN-NEXT: # %bb.4:
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v16, v16
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: .LBB109_5:
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: feq.h a0, fa5, fa5
|
|
; ZVFHMIN-NEXT: fmv.h fa3, fa4
|
|
; ZVFHMIN-NEXT: beqz a0, .LBB109_8
|
|
; ZVFHMIN-NEXT: # %bb.6:
|
|
; ZVFHMIN-NEXT: feq.h a0, fa4, fa4
|
|
; ZVFHMIN-NEXT: beqz a0, .LBB109_9
|
|
; ZVFHMIN-NEXT: .LBB109_7:
|
|
; ZVFHMIN-NEXT: fmin.h fa0, fa5, fa3
|
|
; ZVFHMIN-NEXT: ret
|
|
; ZVFHMIN-NEXT: .LBB109_8:
|
|
; ZVFHMIN-NEXT: fmv.h fa3, fa5
|
|
; ZVFHMIN-NEXT: feq.h a0, fa4, fa4
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB109_7
|
|
; ZVFHMIN-NEXT: .LBB109_9:
|
|
; ZVFHMIN-NEXT: fmin.h fa0, fa4, fa3
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fminimum.v64f16(<64 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fminimum_v64f16_nonans(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fminimum_v64f16_nonans:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fminimum_v64f16_nonans:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmin.vs v12, v16, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v12
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v16, v16
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fmin.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%red = call nnan half @llvm.vector.reduce.fminimum.v64f16(<64 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fminimum_v128f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fminimum_v128f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: addi a1, a0, 128
|
|
; ZVFH-NEXT: li a2, 64
|
|
; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v16, (a0)
|
|
; ZVFH-NEXT: vle16.v v24, (a1)
|
|
; ZVFH-NEXT: vmfeq.vv v0, v16, v16
|
|
; ZVFH-NEXT: vmfeq.vv v7, v24, v24
|
|
; ZVFH-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; ZVFH-NEXT: vmv1r.v v0, v7
|
|
; ZVFH-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; ZVFH-NEXT: vfmin.vv v8, v16, v8
|
|
; ZVFH-NEXT: vmfne.vv v16, v8, v8
|
|
; ZVFH-NEXT: vcpop.m a0, v16
|
|
; ZVFH-NEXT: beqz a0, .LBB111_2
|
|
; ZVFH-NEXT: # %bb.1:
|
|
; ZVFH-NEXT: lui a0, 8
|
|
; ZVFH-NEXT: addi a0, a0, -512
|
|
; ZVFH-NEXT: fmv.h.x fa0, a0
|
|
; ZVFH-NEXT: ret
|
|
; ZVFH-NEXT: .LBB111_2:
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fminimum_v128f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: addi sp, sp, -16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 4
|
|
; ZVFHMIN-NEXT: sub sp, sp, a1
|
|
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
|
|
; ZVFHMIN-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v16, (a0)
|
|
; ZVFHMIN-NEXT: vle16.v v24, (a1)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vmv4r.v v8, v16
|
|
; ZVFHMIN-NEXT: addi a1, sp, 16
|
|
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a0
|
|
; ZVFHMIN-NEXT: vmv4r.v v8, v24
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 3
|
|
; ZVFHMIN-NEXT: add a1, sp, a1
|
|
; ZVFHMIN-NEXT: addi a1, a1, 16
|
|
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
|
|
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
|
|
; ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v8, v8, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfne.vv v16, v8, v8
|
|
; ZVFHMIN-NEXT: vcpop.m a0, v16
|
|
; ZVFHMIN-NEXT: lui a1, 523264
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
|
|
; ZVFHMIN-NEXT: beqz a0, .LBB111_2
|
|
; ZVFHMIN-NEXT: # %bb.1:
|
|
; ZVFHMIN-NEXT: fmv.s fa4, fa5
|
|
; ZVFHMIN-NEXT: j .LBB111_3
|
|
; ZVFHMIN-NEXT: .LBB111_2:
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: .LBB111_3:
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 3
|
|
; ZVFHMIN-NEXT: add a0, sp, a0
|
|
; ZVFHMIN-NEXT: addi a0, a0, 16
|
|
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24
|
|
; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
|
|
; ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
|
|
; ZVFHMIN-NEXT: vfmin.vv v8, v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfne.vv v16, v8, v8
|
|
; ZVFHMIN-NEXT: vcpop.m a0, v16
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB111_5
|
|
; ZVFHMIN-NEXT: # %bb.4:
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: .LBB111_5:
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: feq.h a0, fa5, fa5
|
|
; ZVFHMIN-NEXT: fmv.h fa3, fa4
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB111_7
|
|
; ZVFHMIN-NEXT: # %bb.6:
|
|
; ZVFHMIN-NEXT: fmv.h fa3, fa5
|
|
; ZVFHMIN-NEXT: .LBB111_7:
|
|
; ZVFHMIN-NEXT: feq.h a0, fa4, fa4
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB111_9
|
|
; ZVFHMIN-NEXT: # %bb.8:
|
|
; ZVFHMIN-NEXT: fmv.h fa5, fa4
|
|
; ZVFHMIN-NEXT: .LBB111_9:
|
|
; ZVFHMIN-NEXT: fmin.h fa0, fa5, fa3
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 4
|
|
; ZVFHMIN-NEXT: add sp, sp, a0
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
|
|
; ZVFHMIN-NEXT: addi sp, sp, 16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fminimum.v128f16(<128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fminimum_v128f16_nonans(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fminimum_v128f16_nonans:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: addi a0, a0, 128
|
|
; ZVFH-NEXT: vle16.v v16, (a0)
|
|
; ZVFH-NEXT: vfmin.vv v8, v8, v16
|
|
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fminimum_v128f16_nonans:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: addi sp, sp, -16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 2
|
|
; ZVFHMIN-NEXT: sub sp, sp, a1
|
|
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
|
|
; ZVFHMIN-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v24, (a0)
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a1)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a0
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmin.vv v16, v16, v0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmin.vv v8, v0, v24
|
|
; ZVFHMIN-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmin.vs v16, v16, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v16
|
|
; ZVFHMIN-NEXT: vfredmin.vs v8, v8, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fmin.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 2
|
|
; ZVFHMIN-NEXT: add sp, sp, a0
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
|
|
; ZVFHMIN-NEXT: addi sp, sp, 16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call nnan half @llvm.vector.reduce.fminimum.v128f16(<128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v2f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v9, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v9
|
|
; CHECK-NEXT: beqz a0, .LBB113_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB113_2:
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v2f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v2f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v4f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v9, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v9
|
|
; CHECK-NEXT: beqz a0, .LBB115_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB115_2:
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v4f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v4f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v7f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v7f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v10, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v10
|
|
; CHECK-NEXT: beqz a0, .LBB117_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB117_2:
|
|
; CHECK-NEXT: lui a0, 522240
|
|
; CHECK-NEXT: vmv.s.x v10, a0
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fminimum.v7f32(<7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v7f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v7f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: lui a0, 522240
|
|
; CHECK-NEXT: vmv.s.x v10, a0
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fminimum.v7f32(<7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v8f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v10, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v10
|
|
; CHECK-NEXT: beqz a0, .LBB119_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB119_2:
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v8f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v8f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v16f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v12, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v12
|
|
; CHECK-NEXT: beqz a0, .LBB121_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB121_2:
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v16f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v16f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v32f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v32f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v16, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v16
|
|
; CHECK-NEXT: beqz a0, .LBB123_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB123_2:
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fminimum.v32f32(<32 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v32f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v32f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fminimum.v32f32(<32 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v64f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v64f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi a1, a0, 128
|
|
; CHECK-NEXT: li a2, 32
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: vle32.v v24, (a1)
|
|
; CHECK-NEXT: vmfeq.vv v0, v16, v16
|
|
; CHECK-NEXT: vmfeq.vv v7, v24, v24
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v16, v8
|
|
; CHECK-NEXT: vmfne.vv v16, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v16
|
|
; CHECK-NEXT: beqz a0, .LBB125_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB125_2:
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fminimum.v64f32(<64 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v64f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v64f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fminimum.v64f32(<64 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v128f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v128f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 3
|
|
; CHECK-NEXT: mv a2, a1
|
|
; CHECK-NEXT: slli a1, a1, 1
|
|
; CHECK-NEXT: add a1, a1, a2
|
|
; CHECK-NEXT: sub sp, sp, a1
|
|
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: addi a2, a0, 128
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v24, (a2)
|
|
; CHECK-NEXT: addi a1, a0, 384
|
|
; CHECK-NEXT: vle32.v v8, (a1)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: vle32.v v16, (a1)
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 4
|
|
; CHECK-NEXT: add a1, sp, a1
|
|
; CHECK-NEXT: addi a1, a1, 16
|
|
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
|
|
; CHECK-NEXT: vmfeq.vv v0, v24, v24
|
|
; CHECK-NEXT: vmfeq.vv v7, v8, v8
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vfmin.vv v24, v8, v24
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vmfeq.vv v0, v16, v16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 4
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vmfeq.vv v7, v8, v8
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 4
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 4
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vfmin.vv v16, v16, v8
|
|
; CHECK-NEXT: vmfeq.vv v0, v16, v16
|
|
; CHECK-NEXT: vmfeq.vv v7, v24, v24
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v16, v8
|
|
; CHECK-NEXT: vmfne.vv v16, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v16
|
|
; CHECK-NEXT: beqz a0, .LBB127_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: j .LBB127_3
|
|
; CHECK-NEXT: .LBB127_2:
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: .LBB127_3:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: mv a1, a0
|
|
; CHECK-NEXT: slli a0, a0, 1
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: .cfi_def_cfa sp, 16
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 0
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fminimum.v128f32(<128 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fminimum_v128f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v128f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: addi a2, a0, 384
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a2)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v24, (a0)
|
|
; CHECK-NEXT: vle32.v v0, (a1)
|
|
; CHECK-NEXT: vfmin.vv v8, v24, v8
|
|
; CHECK-NEXT: vfmin.vv v16, v16, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v16, v8
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fminimum.v128f32(<128 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v2f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fminimum_v2f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vle64.v v8, (a0)
|
|
; RV32-NEXT: vmfne.vv v9, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v9
|
|
; RV32-NEXT: beqz a0, .LBB129_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI129_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI129_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB129_2:
|
|
; RV32-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fminimum_v2f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV64-NEXT: vle64.v v8, (a0)
|
|
; RV64-NEXT: vmfne.vv v9, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v9
|
|
; RV64-NEXT: beqz a0, .LBB129_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB129_2:
|
|
; RV64-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v2f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v2f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v4f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fminimum_v4f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vle64.v v8, (a0)
|
|
; RV32-NEXT: vmfne.vv v10, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v10
|
|
; RV32-NEXT: beqz a0, .LBB131_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI131_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI131_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB131_2:
|
|
; RV32-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fminimum_v4f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV64-NEXT: vle64.v v8, (a0)
|
|
; RV64-NEXT: vmfne.vv v10, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v10
|
|
; RV64-NEXT: beqz a0, .LBB131_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB131_2:
|
|
; RV64-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v4f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v4f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v8f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fminimum_v8f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vle64.v v8, (a0)
|
|
; RV32-NEXT: vmfne.vv v12, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v12
|
|
; RV32-NEXT: beqz a0, .LBB133_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI133_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI133_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB133_2:
|
|
; RV32-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fminimum_v8f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV64-NEXT: vle64.v v8, (a0)
|
|
; RV64-NEXT: vmfne.vv v12, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v12
|
|
; RV64-NEXT: beqz a0, .LBB133_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB133_2:
|
|
; RV64-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <8 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fminimum.v8f64(<8 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v8f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v8f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fminimum.v8f64(<8 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v16f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fminimum_v16f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vle64.v v8, (a0)
|
|
; RV32-NEXT: vmfne.vv v16, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v16
|
|
; RV32-NEXT: beqz a0, .LBB135_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI135_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI135_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB135_2:
|
|
; RV32-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fminimum_v16f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vle64.v v8, (a0)
|
|
; RV64-NEXT: vmfne.vv v16, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v16
|
|
; RV64-NEXT: beqz a0, .LBB135_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB135_2:
|
|
; RV64-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <16 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fminimum.v16f64(<16 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v16f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v16f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fminimum.v16f64(<16 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v32f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fminimum_v32f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi a1, a0, 128
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vle64.v v16, (a0)
|
|
; RV32-NEXT: vle64.v v24, (a1)
|
|
; RV32-NEXT: vmfeq.vv v0, v16, v16
|
|
; RV32-NEXT: vmfeq.vv v7, v24, v24
|
|
; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; RV32-NEXT: vmv1r.v v0, v7
|
|
; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; RV32-NEXT: vfmin.vv v8, v16, v8
|
|
; RV32-NEXT: vmfne.vv v16, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v16
|
|
; RV32-NEXT: beqz a0, .LBB137_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI137_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI137_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB137_2:
|
|
; RV32-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fminimum_v32f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi a1, a0, 128
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vle64.v v16, (a0)
|
|
; RV64-NEXT: vle64.v v24, (a1)
|
|
; RV64-NEXT: vmfeq.vv v0, v16, v16
|
|
; RV64-NEXT: vmfeq.vv v7, v24, v24
|
|
; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; RV64-NEXT: vmv1r.v v0, v7
|
|
; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; RV64-NEXT: vfmin.vv v8, v16, v8
|
|
; RV64-NEXT: vmfne.vv v16, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v16
|
|
; RV64-NEXT: beqz a0, .LBB137_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB137_2:
|
|
; RV64-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fminimum.v32f64(<32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v32f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v32f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v16, (a0)
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fminimum.v32f64(<32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v64f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fminimum_v64f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -16
|
|
; RV32-NEXT: .cfi_def_cfa_offset 16
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a1, a1, 3
|
|
; RV32-NEXT: mv a2, a1
|
|
; RV32-NEXT: slli a1, a1, 1
|
|
; RV32-NEXT: add a1, a1, a2
|
|
; RV32-NEXT: sub sp, sp, a1
|
|
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
|
|
; RV32-NEXT: addi a1, a0, 128
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vle64.v v24, (a1)
|
|
; RV32-NEXT: addi a1, a0, 384
|
|
; RV32-NEXT: vle64.v v8, (a1)
|
|
; RV32-NEXT: addi a1, a0, 256
|
|
; RV32-NEXT: vle64.v v16, (a0)
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vmfeq.vv v0, v24, v24
|
|
; RV32-NEXT: vmfeq.vv v7, v8, v8
|
|
; RV32-NEXT: vle64.v v16, (a1)
|
|
; RV32-NEXT: addi a0, sp, 16
|
|
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vmerge.vvm v16, v24, v8, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vmv1r.v v0, v7
|
|
; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vfmin.vv v24, v8, v24
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vmfeq.vv v0, v8, v8
|
|
; RV32-NEXT: addi a0, sp, 16
|
|
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vmfeq.vv v7, v16, v16
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vmv1r.v v0, v7
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vfmin.vv v16, v16, v8
|
|
; RV32-NEXT: vmfeq.vv v0, v16, v16
|
|
; RV32-NEXT: vmfeq.vv v7, v24, v24
|
|
; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; RV32-NEXT: vmv1r.v v0, v7
|
|
; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; RV32-NEXT: vfmin.vv v8, v16, v8
|
|
; RV32-NEXT: vmfne.vv v16, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v16
|
|
; RV32-NEXT: beqz a0, .LBB139_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI139_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI139_0)(a0)
|
|
; RV32-NEXT: j .LBB139_3
|
|
; RV32-NEXT: .LBB139_2:
|
|
; RV32-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: .LBB139_3:
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: mv a1, a0
|
|
; RV32-NEXT: slli a0, a0, 1
|
|
; RV32-NEXT: add a0, a0, a1
|
|
; RV32-NEXT: add sp, sp, a0
|
|
; RV32-NEXT: .cfi_def_cfa sp, 16
|
|
; RV32-NEXT: addi sp, sp, 16
|
|
; RV32-NEXT: .cfi_def_cfa_offset 0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fminimum_v64f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -16
|
|
; RV64-NEXT: .cfi_def_cfa_offset 16
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: slli a1, a1, 3
|
|
; RV64-NEXT: mv a2, a1
|
|
; RV64-NEXT: slli a1, a1, 1
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: sub sp, sp, a1
|
|
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
|
|
; RV64-NEXT: addi a1, a0, 128
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vle64.v v24, (a1)
|
|
; RV64-NEXT: addi a1, a0, 384
|
|
; RV64-NEXT: vle64.v v8, (a1)
|
|
; RV64-NEXT: addi a1, a0, 256
|
|
; RV64-NEXT: vle64.v v16, (a0)
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 4
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV64-NEXT: vmfeq.vv v0, v24, v24
|
|
; RV64-NEXT: vmfeq.vv v7, v8, v8
|
|
; RV64-NEXT: vle64.v v16, (a1)
|
|
; RV64-NEXT: addi a0, sp, 16
|
|
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV64-NEXT: vmerge.vvm v16, v24, v8, v0
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV64-NEXT: vmv1r.v v0, v7
|
|
; RV64-NEXT: vmerge.vvm v8, v8, v24, v0
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vfmin.vv v24, v8, v24
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 4
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vmfeq.vv v0, v8, v8
|
|
; RV64-NEXT: addi a0, sp, 16
|
|
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vmfeq.vv v7, v16, v16
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 4
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
|
; RV64-NEXT: vmv1r.v v0, v7
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 4
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vfmin.vv v16, v16, v8
|
|
; RV64-NEXT: vmfeq.vv v0, v16, v16
|
|
; RV64-NEXT: vmfeq.vv v7, v24, v24
|
|
; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; RV64-NEXT: vmv1r.v v0, v7
|
|
; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; RV64-NEXT: vfmin.vv v8, v16, v8
|
|
; RV64-NEXT: vmfne.vv v16, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v16
|
|
; RV64-NEXT: beqz a0, .LBB139_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: j .LBB139_3
|
|
; RV64-NEXT: .LBB139_2:
|
|
; RV64-NEXT: vfredmin.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: .LBB139_3:
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: mv a1, a0
|
|
; RV64-NEXT: slli a0, a0, 1
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: add sp, sp, a0
|
|
; RV64-NEXT: .cfi_def_cfa sp, 16
|
|
; RV64-NEXT: addi sp, sp, 16
|
|
; RV64-NEXT: .cfi_def_cfa_offset 0
|
|
; RV64-NEXT: ret
|
|
%v = load <64 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fminimum.v64f64(<64 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fminimum_v64f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fminimum_v64f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a1, a0, 384
|
|
; CHECK-NEXT: vle64.v v16, (a1)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v24, (a0)
|
|
; CHECK-NEXT: vle64.v v0, (a1)
|
|
; CHECK-NEXT: vfmin.vv v16, v24, v16
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fminimum.v64f64(<64 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define half @vreduce_fmaximum_v64f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmaximum_v64f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vmfne.vv v16, v8, v8
|
|
; ZVFH-NEXT: vcpop.m a0, v16
|
|
; ZVFH-NEXT: beqz a0, .LBB141_2
|
|
; ZVFH-NEXT: # %bb.1:
|
|
; ZVFH-NEXT: lui a0, 8
|
|
; ZVFH-NEXT: addi a0, a0, -512
|
|
; ZVFH-NEXT: fmv.h.x fa0, a0
|
|
; ZVFH-NEXT: ret
|
|
; ZVFH-NEXT: .LBB141_2:
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmaximum_v64f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v24, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfne.vv v12, v16, v16
|
|
; ZVFHMIN-NEXT: vcpop.m a0, v12
|
|
; ZVFHMIN-NEXT: lui a1, 523264
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
|
|
; ZVFHMIN-NEXT: beqz a0, .LBB141_2
|
|
; ZVFHMIN-NEXT: # %bb.1:
|
|
; ZVFHMIN-NEXT: fmv.s fa4, fa5
|
|
; ZVFHMIN-NEXT: j .LBB141_3
|
|
; ZVFHMIN-NEXT: .LBB141_2:
|
|
; ZVFHMIN-NEXT: vfredmax.vs v12, v16, v16
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v12
|
|
; ZVFHMIN-NEXT: .LBB141_3:
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfne.vv v8, v16, v16
|
|
; ZVFHMIN-NEXT: vcpop.m a0, v8
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB141_5
|
|
; ZVFHMIN-NEXT: # %bb.4:
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v16, v16
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: .LBB141_5:
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: feq.h a0, fa5, fa5
|
|
; ZVFHMIN-NEXT: fmv.h fa3, fa4
|
|
; ZVFHMIN-NEXT: beqz a0, .LBB141_8
|
|
; ZVFHMIN-NEXT: # %bb.6:
|
|
; ZVFHMIN-NEXT: feq.h a0, fa4, fa4
|
|
; ZVFHMIN-NEXT: beqz a0, .LBB141_9
|
|
; ZVFHMIN-NEXT: .LBB141_7:
|
|
; ZVFHMIN-NEXT: fmax.h fa0, fa5, fa3
|
|
; ZVFHMIN-NEXT: ret
|
|
; ZVFHMIN-NEXT: .LBB141_8:
|
|
; ZVFHMIN-NEXT: fmv.h fa3, fa5
|
|
; ZVFHMIN-NEXT: feq.h a0, fa4, fa4
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB141_7
|
|
; ZVFHMIN-NEXT: .LBB141_9:
|
|
; ZVFHMIN-NEXT: fmax.h fa0, fa4, fa3
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmaximum.v64f16(<64 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmaximum_v64f16_nonans(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmaximum_v64f16_nonans:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmaximum_v64f16_nonans:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: li a1, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a0)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmax.vs v12, v16, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v12
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v16, v16
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fmax.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%red = call nnan half @llvm.vector.reduce.fmaximum.v64f16(<64 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmaximum_v128f16(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmaximum_v128f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: addi a1, a0, 128
|
|
; ZVFH-NEXT: li a2, 64
|
|
; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v16, (a0)
|
|
; ZVFH-NEXT: vle16.v v24, (a1)
|
|
; ZVFH-NEXT: vmfeq.vv v0, v16, v16
|
|
; ZVFH-NEXT: vmfeq.vv v7, v24, v24
|
|
; ZVFH-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; ZVFH-NEXT: vmv1r.v v0, v7
|
|
; ZVFH-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; ZVFH-NEXT: vfmax.vv v8, v16, v8
|
|
; ZVFH-NEXT: vmfne.vv v16, v8, v8
|
|
; ZVFH-NEXT: vcpop.m a0, v16
|
|
; ZVFH-NEXT: beqz a0, .LBB143_2
|
|
; ZVFH-NEXT: # %bb.1:
|
|
; ZVFH-NEXT: lui a0, 8
|
|
; ZVFH-NEXT: addi a0, a0, -512
|
|
; ZVFH-NEXT: fmv.h.x fa0, a0
|
|
; ZVFH-NEXT: ret
|
|
; ZVFH-NEXT: .LBB143_2:
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmaximum_v128f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: addi sp, sp, -16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 4
|
|
; ZVFHMIN-NEXT: sub sp, sp, a1
|
|
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
|
|
; ZVFHMIN-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v16, (a0)
|
|
; ZVFHMIN-NEXT: vle16.v v24, (a1)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vmv4r.v v8, v16
|
|
; ZVFHMIN-NEXT: addi a1, sp, 16
|
|
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a0
|
|
; ZVFHMIN-NEXT: vmv4r.v v8, v24
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 3
|
|
; ZVFHMIN-NEXT: add a1, sp, a1
|
|
; ZVFHMIN-NEXT: addi a1, a1, 16
|
|
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
|
|
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
|
|
; ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; ZVFHMIN-NEXT: vfmax.vv v8, v8, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfne.vv v16, v8, v8
|
|
; ZVFHMIN-NEXT: vcpop.m a0, v16
|
|
; ZVFHMIN-NEXT: lui a1, 523264
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
|
|
; ZVFHMIN-NEXT: beqz a0, .LBB143_2
|
|
; ZVFHMIN-NEXT: # %bb.1:
|
|
; ZVFHMIN-NEXT: fmv.s fa4, fa5
|
|
; ZVFHMIN-NEXT: j .LBB143_3
|
|
; ZVFHMIN-NEXT: .LBB143_2:
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: .LBB143_3:
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 3
|
|
; ZVFHMIN-NEXT: add a0, sp, a0
|
|
; ZVFHMIN-NEXT: addi a0, a0, 16
|
|
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24
|
|
; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
|
|
; ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
|
|
; ZVFHMIN-NEXT: vfmax.vv v8, v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfne.vv v16, v8, v8
|
|
; ZVFHMIN-NEXT: vcpop.m a0, v16
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB143_5
|
|
; ZVFHMIN-NEXT: # %bb.4:
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
|
|
; ZVFHMIN-NEXT: .LBB143_5:
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: feq.h a0, fa5, fa5
|
|
; ZVFHMIN-NEXT: fmv.h fa3, fa4
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB143_7
|
|
; ZVFHMIN-NEXT: # %bb.6:
|
|
; ZVFHMIN-NEXT: fmv.h fa3, fa5
|
|
; ZVFHMIN-NEXT: .LBB143_7:
|
|
; ZVFHMIN-NEXT: feq.h a0, fa4, fa4
|
|
; ZVFHMIN-NEXT: bnez a0, .LBB143_9
|
|
; ZVFHMIN-NEXT: # %bb.8:
|
|
; ZVFHMIN-NEXT: fmv.h fa5, fa4
|
|
; ZVFHMIN-NEXT: .LBB143_9:
|
|
; ZVFHMIN-NEXT: fmax.h fa0, fa5, fa3
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 4
|
|
; ZVFHMIN-NEXT: add sp, sp, a0
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
|
|
; ZVFHMIN-NEXT: addi sp, sp, 16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmaximum.v128f16(<128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmaximum_v128f16_nonans(ptr %x) {
|
|
; ZVFH-LABEL: vreduce_fmaximum_v128f16_nonans:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: li a1, 64
|
|
; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vle16.v v8, (a0)
|
|
; ZVFH-NEXT: addi a0, a0, 128
|
|
; ZVFH-NEXT: vle16.v v16, (a0)
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v16
|
|
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFH-NEXT: vfmv.f.s fa0, v8
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vreduce_fmaximum_v128f16_nonans:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: addi sp, sp, -16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
|
|
; ZVFHMIN-NEXT: csrr a1, vlenb
|
|
; ZVFHMIN-NEXT: slli a1, a1, 2
|
|
; ZVFHMIN-NEXT: sub sp, sp, a1
|
|
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
|
|
; ZVFHMIN-NEXT: addi a1, a0, 128
|
|
; ZVFHMIN-NEXT: li a2, 64
|
|
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vle16.v v24, (a0)
|
|
; ZVFHMIN-NEXT: vle16.v v8, (a1)
|
|
; ZVFHMIN-NEXT: li a0, 32
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a0
|
|
; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
|
|
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmax.vv v8, v0, v24
|
|
; ZVFHMIN-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfredmax.vs v16, v16, v16
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa5, v16
|
|
; ZVFHMIN-NEXT: vfredmax.vs v8, v8, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
|
|
; ZVFHMIN-NEXT: vfmv.f.s fa4, v8
|
|
; ZVFHMIN-NEXT: fcvt.h.s fa4, fa4
|
|
; ZVFHMIN-NEXT: fmax.h fa0, fa5, fa4
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 2
|
|
; ZVFHMIN-NEXT: add sp, sp, a0
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
|
|
; ZVFHMIN-NEXT: addi sp, sp, 16
|
|
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call nnan half @llvm.vector.reduce.fmaximum.v128f16(<128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v2f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v9, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v9
|
|
; CHECK-NEXT: beqz a0, .LBB145_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB145_2:
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v2f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v2f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v4f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v9, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v9
|
|
; CHECK-NEXT: beqz a0, .LBB147_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB147_2:
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v4f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v4f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v7f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v7f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v10, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v10
|
|
; CHECK-NEXT: beqz a0, .LBB149_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB149_2:
|
|
; CHECK-NEXT: lui a0, 1046528
|
|
; CHECK-NEXT: vmv.s.x v10, a0
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmaximum.v7f32(<7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v7f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v7f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: lui a0, 1046528
|
|
; CHECK-NEXT: vmv.s.x v10, a0
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <7 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmaximum.v7f32(<7 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v8f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v10, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v10
|
|
; CHECK-NEXT: beqz a0, .LBB151_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB151_2:
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v8f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v8f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v16f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v12, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v12
|
|
; CHECK-NEXT: beqz a0, .LBB153_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB153_2:
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v16f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v16f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v32f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v32f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vmfne.vv v16, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v16
|
|
; CHECK-NEXT: beqz a0, .LBB155_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB155_2:
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v32f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v32f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v64f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v64f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi a1, a0, 128
|
|
; CHECK-NEXT: li a2, 32
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: vle32.v v24, (a1)
|
|
; CHECK-NEXT: vmfeq.vv v0, v16, v16
|
|
; CHECK-NEXT: vmfeq.vv v7, v24, v24
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v16, v8
|
|
; CHECK-NEXT: vmfne.vv v16, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v16
|
|
; CHECK-NEXT: beqz a0, .LBB157_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB157_2:
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v64f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v64f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v128f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v128f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 3
|
|
; CHECK-NEXT: mv a2, a1
|
|
; CHECK-NEXT: slli a1, a1, 1
|
|
; CHECK-NEXT: add a1, a1, a2
|
|
; CHECK-NEXT: sub sp, sp, a1
|
|
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: addi a2, a0, 128
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v24, (a2)
|
|
; CHECK-NEXT: addi a1, a0, 384
|
|
; CHECK-NEXT: vle32.v v8, (a1)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: vle32.v v16, (a1)
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 4
|
|
; CHECK-NEXT: add a1, sp, a1
|
|
; CHECK-NEXT: addi a1, a1, 16
|
|
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
|
|
; CHECK-NEXT: vmfeq.vv v0, v24, v24
|
|
; CHECK-NEXT: vmfeq.vv v7, v8, v8
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vfmax.vv v24, v8, v24
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vmfeq.vv v0, v16, v16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 4
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vmfeq.vv v7, v8, v8
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 4
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 4
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vfmax.vv v16, v16, v8
|
|
; CHECK-NEXT: vmfeq.vv v0, v16, v16
|
|
; CHECK-NEXT: vmfeq.vv v7, v24, v24
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v16, v8
|
|
; CHECK-NEXT: vmfne.vv v16, v8, v8
|
|
; CHECK-NEXT: vcpop.m a0, v16
|
|
; CHECK-NEXT: beqz a0, .LBB159_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: lui a0, 523264
|
|
; CHECK-NEXT: fmv.w.x fa0, a0
|
|
; CHECK-NEXT: j .LBB159_3
|
|
; CHECK-NEXT: .LBB159_2:
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: .LBB159_3:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a0, a0, 3
|
|
; CHECK-NEXT: mv a1, a0
|
|
; CHECK-NEXT: slli a0, a0, 1
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: .cfi_def_cfa sp, 16
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 0
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmaximum_v128f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v128f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: addi a2, a0, 384
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a2)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v24, (a0)
|
|
; CHECK-NEXT: vle32.v v0, (a1)
|
|
; CHECK-NEXT: vfmax.vv v8, v24, v8
|
|
; CHECK-NEXT: vfmax.vv v16, v16, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v16, v8
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v2f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fmaximum_v2f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV32-NEXT: vle64.v v8, (a0)
|
|
; RV32-NEXT: vmfne.vv v9, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v9
|
|
; RV32-NEXT: beqz a0, .LBB161_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI161_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI161_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB161_2:
|
|
; RV32-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fmaximum_v2f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; RV64-NEXT: vle64.v v8, (a0)
|
|
; RV64-NEXT: vmfne.vv v9, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v9
|
|
; RV64-NEXT: beqz a0, .LBB161_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB161_2:
|
|
; RV64-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v2f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v2f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v4f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fmaximum_v4f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV32-NEXT: vle64.v v8, (a0)
|
|
; RV32-NEXT: vmfne.vv v10, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v10
|
|
; RV32-NEXT: beqz a0, .LBB163_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI163_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI163_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB163_2:
|
|
; RV32-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fmaximum_v4f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; RV64-NEXT: vle64.v v8, (a0)
|
|
; RV64-NEXT: vmfne.vv v10, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v10
|
|
; RV64-NEXT: beqz a0, .LBB163_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB163_2:
|
|
; RV64-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v4f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v4f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v8f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fmaximum_v8f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV32-NEXT: vle64.v v8, (a0)
|
|
; RV32-NEXT: vmfne.vv v12, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v12
|
|
; RV32-NEXT: beqz a0, .LBB165_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI165_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI165_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB165_2:
|
|
; RV32-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fmaximum_v8f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; RV64-NEXT: vle64.v v8, (a0)
|
|
; RV64-NEXT: vmfne.vv v12, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v12
|
|
; RV64-NEXT: beqz a0, .LBB165_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB165_2:
|
|
; RV64-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <8 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v8f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v8f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v16f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fmaximum_v16f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vle64.v v8, (a0)
|
|
; RV32-NEXT: vmfne.vv v16, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v16
|
|
; RV32-NEXT: beqz a0, .LBB167_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI167_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI167_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB167_2:
|
|
; RV32-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fmaximum_v16f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vle64.v v8, (a0)
|
|
; RV64-NEXT: vmfne.vv v16, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v16
|
|
; RV64-NEXT: beqz a0, .LBB167_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB167_2:
|
|
; RV64-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <16 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v16f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v16f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v32f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fmaximum_v32f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi a1, a0, 128
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vle64.v v16, (a0)
|
|
; RV32-NEXT: vle64.v v24, (a1)
|
|
; RV32-NEXT: vmfeq.vv v0, v16, v16
|
|
; RV32-NEXT: vmfeq.vv v7, v24, v24
|
|
; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; RV32-NEXT: vmv1r.v v0, v7
|
|
; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; RV32-NEXT: vfmax.vv v8, v16, v8
|
|
; RV32-NEXT: vmfne.vv v16, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v16
|
|
; RV32-NEXT: beqz a0, .LBB169_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI169_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI169_0)(a0)
|
|
; RV32-NEXT: ret
|
|
; RV32-NEXT: .LBB169_2:
|
|
; RV32-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fmaximum_v32f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi a1, a0, 128
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vle64.v v16, (a0)
|
|
; RV64-NEXT: vle64.v v24, (a1)
|
|
; RV64-NEXT: vmfeq.vv v0, v16, v16
|
|
; RV64-NEXT: vmfeq.vv v7, v24, v24
|
|
; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; RV64-NEXT: vmv1r.v v0, v7
|
|
; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; RV64-NEXT: vfmax.vv v8, v16, v8
|
|
; RV64-NEXT: vmfne.vv v16, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v16
|
|
; RV64-NEXT: beqz a0, .LBB169_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: ret
|
|
; RV64-NEXT: .LBB169_2:
|
|
; RV64-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v32f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v32f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v16, (a0)
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v64f64(ptr %x) {
|
|
; RV32-LABEL: vreduce_fmaximum_v64f64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -16
|
|
; RV32-NEXT: .cfi_def_cfa_offset 16
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a1, a1, 3
|
|
; RV32-NEXT: mv a2, a1
|
|
; RV32-NEXT: slli a1, a1, 1
|
|
; RV32-NEXT: add a1, a1, a2
|
|
; RV32-NEXT: sub sp, sp, a1
|
|
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
|
|
; RV32-NEXT: addi a1, a0, 128
|
|
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV32-NEXT: vle64.v v24, (a1)
|
|
; RV32-NEXT: addi a1, a0, 384
|
|
; RV32-NEXT: vle64.v v8, (a1)
|
|
; RV32-NEXT: addi a1, a0, 256
|
|
; RV32-NEXT: vle64.v v16, (a0)
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vmfeq.vv v0, v24, v24
|
|
; RV32-NEXT: vmfeq.vv v7, v8, v8
|
|
; RV32-NEXT: vle64.v v16, (a1)
|
|
; RV32-NEXT: addi a0, sp, 16
|
|
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vmerge.vvm v16, v24, v8, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vmv1r.v v0, v7
|
|
; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vfmax.vv v24, v8, v24
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vmfeq.vv v0, v8, v8
|
|
; RV32-NEXT: addi a0, sp, 16
|
|
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vmfeq.vv v7, v16, v16
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
|
; RV32-NEXT: vmv1r.v v0, v7
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 4
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 16
|
|
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV32-NEXT: vfmax.vv v16, v16, v8
|
|
; RV32-NEXT: vmfeq.vv v0, v16, v16
|
|
; RV32-NEXT: vmfeq.vv v7, v24, v24
|
|
; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; RV32-NEXT: vmv1r.v v0, v7
|
|
; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; RV32-NEXT: vfmax.vv v8, v16, v8
|
|
; RV32-NEXT: vmfne.vv v16, v8, v8
|
|
; RV32-NEXT: vcpop.m a0, v16
|
|
; RV32-NEXT: beqz a0, .LBB171_2
|
|
; RV32-NEXT: # %bb.1:
|
|
; RV32-NEXT: lui a0, %hi(.LCPI171_0)
|
|
; RV32-NEXT: fld fa0, %lo(.LCPI171_0)(a0)
|
|
; RV32-NEXT: j .LBB171_3
|
|
; RV32-NEXT: .LBB171_2:
|
|
; RV32-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV32-NEXT: vfmv.f.s fa0, v8
|
|
; RV32-NEXT: .LBB171_3:
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 3
|
|
; RV32-NEXT: mv a1, a0
|
|
; RV32-NEXT: slli a0, a0, 1
|
|
; RV32-NEXT: add a0, a0, a1
|
|
; RV32-NEXT: add sp, sp, a0
|
|
; RV32-NEXT: .cfi_def_cfa sp, 16
|
|
; RV32-NEXT: addi sp, sp, 16
|
|
; RV32-NEXT: .cfi_def_cfa_offset 0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vreduce_fmaximum_v64f64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -16
|
|
; RV64-NEXT: .cfi_def_cfa_offset 16
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: slli a1, a1, 3
|
|
; RV64-NEXT: mv a2, a1
|
|
; RV64-NEXT: slli a1, a1, 1
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: sub sp, sp, a1
|
|
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
|
|
; RV64-NEXT: addi a1, a0, 128
|
|
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; RV64-NEXT: vle64.v v24, (a1)
|
|
; RV64-NEXT: addi a1, a0, 384
|
|
; RV64-NEXT: vle64.v v8, (a1)
|
|
; RV64-NEXT: addi a1, a0, 256
|
|
; RV64-NEXT: vle64.v v16, (a0)
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 4
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV64-NEXT: vmfeq.vv v0, v24, v24
|
|
; RV64-NEXT: vmfeq.vv v7, v8, v8
|
|
; RV64-NEXT: vle64.v v16, (a1)
|
|
; RV64-NEXT: addi a0, sp, 16
|
|
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV64-NEXT: vmerge.vvm v16, v24, v8, v0
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
|
; RV64-NEXT: vmv1r.v v0, v7
|
|
; RV64-NEXT: vmerge.vvm v8, v8, v24, v0
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vfmax.vv v24, v8, v24
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 4
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vmfeq.vv v0, v8, v8
|
|
; RV64-NEXT: addi a0, sp, 16
|
|
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vmfeq.vv v7, v16, v16
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 4
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
|
; RV64-NEXT: vmv1r.v v0, v7
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 4
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 16
|
|
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
|
; RV64-NEXT: vfmax.vv v16, v16, v8
|
|
; RV64-NEXT: vmfeq.vv v0, v16, v16
|
|
; RV64-NEXT: vmfeq.vv v7, v24, v24
|
|
; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
|
|
; RV64-NEXT: vmv1r.v v0, v7
|
|
; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
|
|
; RV64-NEXT: vfmax.vv v8, v16, v8
|
|
; RV64-NEXT: vmfne.vv v16, v8, v8
|
|
; RV64-NEXT: vcpop.m a0, v16
|
|
; RV64-NEXT: beqz a0, .LBB171_2
|
|
; RV64-NEXT: # %bb.1:
|
|
; RV64-NEXT: lui a0, 4095
|
|
; RV64-NEXT: slli a0, a0, 39
|
|
; RV64-NEXT: fmv.d.x fa0, a0
|
|
; RV64-NEXT: j .LBB171_3
|
|
; RV64-NEXT: .LBB171_2:
|
|
; RV64-NEXT: vfredmax.vs v8, v8, v8
|
|
; RV64-NEXT: vfmv.f.s fa0, v8
|
|
; RV64-NEXT: .LBB171_3:
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 3
|
|
; RV64-NEXT: mv a1, a0
|
|
; RV64-NEXT: slli a0, a0, 1
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: add sp, sp, a0
|
|
; RV64-NEXT: .cfi_def_cfa sp, 16
|
|
; RV64-NEXT: addi sp, sp, 16
|
|
; RV64-NEXT: .cfi_def_cfa_offset 0
|
|
; RV64-NEXT: ret
|
|
%v = load <64 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmaximum_v64f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmaximum_v64f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a1, a0, 384
|
|
; CHECK-NEXT: vle64.v v16, (a1)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v24, (a0)
|
|
; CHECK-NEXT: vle64.v v0, (a1)
|
|
; CHECK-NEXT: vfmax.vv v16, v24, v16
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> %v)
|
|
ret double %red
|
|
}
|