derek.holloway
7502bf64a4
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361 lines
13 KiB
LLVM
361 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN
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define <4 x half> @vsitofp_v4f16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vsitofp_v4f16_v4i7:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; ZVFH-NEXT: vadd.vv v8, v8, v8
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; ZVFH-NEXT: vsra.vi v9, v8, 1
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; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vsitofp_v4f16_v4i7:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; ZVFHMIN-NEXT: vadd.vv v8, v8, v8
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; ZVFHMIN-NEXT: vsra.vi v8, v8, 1
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vsext.vf2 v9, v8
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; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v9
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
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; ZVFHMIN-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i7(<4 x i7> %va, <4 x i1> %m, i32 %evl)
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ret <4 x half> %v
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}
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define <4 x half> @vsitofp_v4f16_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vsitofp_v4f16_v4i8:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; ZVFH-NEXT: vfwcvt.f.x.v v9, v8
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; ZVFH-NEXT: vmv1r.v v8, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vsitofp_v4f16_v4i8:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vsext.vf2 v9, v8
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; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v9
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
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; ZVFHMIN-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
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ret <4 x half> %v
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}
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define <4 x half> @vsitofp_v4f16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
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; ZVFH-LABEL: vsitofp_v4f16_v4i8_unmasked:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; ZVFH-NEXT: vfwcvt.f.x.v v9, v8
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; ZVFH-NEXT: vmv1r.v v8, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vsitofp_v4f16_v4i8_unmasked:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vsext.vf2 v9, v8
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; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v9
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
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; ZVFHMIN-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x half> %v
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}
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define <4 x half> @vsitofp_v4f16_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vsitofp_v4f16_v4i16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH-NEXT: vfcvt.f.x.v v8, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vsitofp_v4f16_v4i16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
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; ZVFHMIN-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
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ret <4 x half> %v
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}
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define <4 x half> @vsitofp_v4f16_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
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; ZVFH-LABEL: vsitofp_v4f16_v4i16_unmasked:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH-NEXT: vfcvt.f.x.v v8, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vsitofp_v4f16_v4i16_unmasked:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
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; ZVFHMIN-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x half> %v
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}
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define <4 x half> @vsitofp_v4f16_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vsitofp_v4f16_v4i32:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH-NEXT: vfncvt.f.x.w v9, v8
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; ZVFH-NEXT: vmv1r.v v8, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vsitofp_v4f16_v4i32:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vfcvt.f.x.v v9, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
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; ZVFHMIN-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
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ret <4 x half> %v
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}
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define <4 x half> @vsitofp_v4f16_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
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; ZVFH-LABEL: vsitofp_v4f16_v4i32_unmasked:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH-NEXT: vfncvt.f.x.w v9, v8
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; ZVFH-NEXT: vmv1r.v v8, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vsitofp_v4f16_v4i32_unmasked:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vfcvt.f.x.v v9, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
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; ZVFHMIN-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x half> %v
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}
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define <4 x half> @vsitofp_v4f16_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f16_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfncvt.f.x.w v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vfncvt.f.f.w v8, v10
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; CHECK-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
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ret <4 x half> %v
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}
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define <4 x half> @vsitofp_v4f16_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f16_v4i64_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfncvt.f.x.w v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vfncvt.f.f.w v8, v10
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; CHECK-NEXT: ret
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%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x half> %v
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}
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define <4 x float> @vsitofp_v4f32_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f32_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vsext.vf2 v9, v8
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; CHECK-NEXT: vfwcvt.f.x.v v8, v9
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; CHECK-NEXT: ret
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%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
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ret <4 x float> %v
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}
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define <4 x float> @vsitofp_v4f32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f32_v4i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vsext.vf2 v9, v8
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; CHECK-NEXT: vfwcvt.f.x.v v8, v9
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; CHECK-NEXT: ret
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%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x float> %v
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}
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define <4 x float> @vsitofp_v4f32_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f32_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.x.v v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
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ret <4 x float> %v
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}
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define <4 x float> @vsitofp_v4f32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f32_v4i16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.x.v v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x float> %v
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}
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define <4 x float> @vsitofp_v4f32_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f32_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfcvt.f.x.v v8, v8
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; CHECK-NEXT: ret
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%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
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ret <4 x float> %v
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}
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define <4 x float> @vsitofp_v4f32_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f32_v4i32_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfcvt.f.x.v v8, v8
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; CHECK-NEXT: ret
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%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x float> %v
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}
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define <4 x float> @vsitofp_v4f32_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f32_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfncvt.f.x.w v10, v8
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
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ret <4 x float> %v
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}
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define <4 x float> @vsitofp_v4f32_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f32_v4i64_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfncvt.f.x.w v10, v8
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x float> %v
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}
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define <4 x double> @vsitofp_v4f64_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f64_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vsext.vf4 v10, v8
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; CHECK-NEXT: vfwcvt.f.x.v v8, v10
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; CHECK-NEXT: ret
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%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
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ret <4 x double> %v
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}
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define <4 x double> @vsitofp_v4f64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsitofp_v4f64_v4i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vsext.vf4 v10, v8
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; CHECK-NEXT: vfwcvt.f.x.v v8, v10
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; CHECK-NEXT: ret
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%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x double> %v
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}
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|
|
|
define <4 x double> @vsitofp_v4f64_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsitofp_v4f64_v4i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsext.vf2 v10, v8
|
|
; CHECK-NEXT: vfwcvt.f.x.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
|
|
ret <4 x double> %v
|
|
}
|
|
|
|
define <4 x double> @vsitofp_v4f64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsitofp_v4f64_v4i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsext.vf2 v10, v8
|
|
; CHECK-NEXT: vfwcvt.f.x.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x double> %v
|
|
}
|
|
|
|
define <4 x double> @vsitofp_v4f64_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsitofp_v4f64_v4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vmv1r.v v10, v8
|
|
; CHECK-NEXT: vfwcvt.f.x.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
|
|
ret <4 x double> %v
|
|
}
|
|
|
|
define <4 x double> @vsitofp_v4f64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsitofp_v4f64_v4i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vmv1r.v v10, v8
|
|
; CHECK-NEXT: vfwcvt.f.x.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x double> %v
|
|
}
|
|
|
|
define <4 x double> @vsitofp_v4f64_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsitofp_v4f64_v4i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
|
|
ret <4 x double> %v
|
|
}
|
|
|
|
define <4 x double> @vsitofp_v4f64_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsitofp_v4f64_v4i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x double> %v
|
|
}
|
|
|
|
define <32 x double> @vsitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsitofp_v32f64_v32i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
|
; CHECK-NEXT: vfcvt.f.x.v v16, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
|
|
ret <32 x double> %v
|
|
}
|
|
|
|
define <32 x double> @vsitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsitofp_v32f64_v32i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfcvt.f.x.v v8, v8
|
|
; CHECK-NEXT: vfcvt.f.x.v v16, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> splat (i1 true), i32 %evl)
|
|
ret <32 x double> %v
|
|
}
|