derek.holloway
7502bf64a4
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87 lines
3.2 KiB
LLVM
87 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
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; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
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define <8 x i8> @not_signbit_mask_v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: not_signbit_mask_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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;
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; CHECK-ZVKB-LABEL: not_signbit_mask_v8i8:
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; CHECK-ZVKB: # %bb.0:
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; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 7
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; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
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; CHECK-ZVKB-NEXT: ret
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%cond = icmp sgt <8 x i8> %a, splat (i8 -1)
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%r = select <8 x i1> %cond, <8 x i8> %b, <8 x i8> zeroinitializer
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ret <8 x i8> %r
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}
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define <4 x i16> @not_signbit_mask_v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: not_signbit_mask_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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;
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; CHECK-ZVKB-LABEL: not_signbit_mask_v4i16:
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; CHECK-ZVKB: # %bb.0:
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; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 15
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; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
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; CHECK-ZVKB-NEXT: ret
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%cond = icmp sgt <4 x i16> %a, splat (i16 -1)
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%r = select <4 x i1> %cond, <4 x i16> %b, <4 x i16> zeroinitializer
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ret <4 x i16> %r
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}
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define <2 x i32> @not_signbit_mask_v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: not_signbit_mask_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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;
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; CHECK-ZVKB-LABEL: not_signbit_mask_v2i32:
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; CHECK-ZVKB: # %bb.0:
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; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 31
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; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
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; CHECK-ZVKB-NEXT: ret
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%cond = icmp sgt <2 x i32> %a, splat (i32 -1)
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%r = select <2 x i1> %cond, <2 x i32> %b, <2 x i32> zeroinitializer
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ret <2 x i32> %r
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}
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define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: not_signbit_mask_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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;
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; CHECK-ZVKB-LABEL: not_signbit_mask_v2i64:
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; CHECK-ZVKB: # %bb.0:
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; CHECK-ZVKB-NEXT: li a0, 63
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; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; CHECK-ZVKB-NEXT: vsra.vx v8, v8, a0
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; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
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; CHECK-ZVKB-NEXT: ret
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%cond = icmp sgt <2 x i64> %a, splat (i64 -1)
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%r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer
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ret <2 x i64> %r
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}
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