derek.holloway
7502bf64a4
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357 lines
12 KiB
LLVM
357 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+experimental-zvfbfa,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+experimental-zvfbfa,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
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define <2 x i1> @isnan_v2bf16(<2 x bfloat> %x) {
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; ZVFBFMIN-LABEL: isnan_v2bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: lui a0, 8
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; ZVFBFMIN-NEXT: addi a1, a0, -1
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; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFBFMIN-NEXT: vand.vx v8, v8, a1
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; ZVFBFMIN-NEXT: addi a0, a0, -128
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; ZVFBFMIN-NEXT: vmsgt.vx v0, v8, a0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: isnan_v2bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: li a0, 768
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; ZVFBFA-NEXT: vand.vx v8, v8, a0
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; ZVFBFA-NEXT: vmsne.vi v0, v8, 0
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; ZVFBFA-NEXT: ret
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%1 = call <2 x i1> @llvm.is.fpclass.v2bf16(<2 x bfloat> %x, i32 3) ; nan
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ret <2 x i1> %1
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}
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define <4 x i1> @isnan_v4bf16(<4 x bfloat> %x) {
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; ZVFBFMIN-LABEL: isnan_v4bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: lui a0, 8
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; ZVFBFMIN-NEXT: addi a1, a0, -1
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; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFBFMIN-NEXT: vand.vx v8, v8, a1
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; ZVFBFMIN-NEXT: addi a0, a0, -128
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; ZVFBFMIN-NEXT: vmsgt.vx v0, v8, a0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: isnan_v4bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: li a0, 768
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; ZVFBFA-NEXT: vand.vx v8, v8, a0
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; ZVFBFA-NEXT: vmsne.vi v0, v8, 0
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; ZVFBFA-NEXT: ret
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%1 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> %x, i32 3) ; nan
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ret <4 x i1> %1
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}
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define <8 x i1> @isnan_v8bf16(<8 x bfloat> %x) {
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; ZVFBFMIN-LABEL: isnan_v8bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: lui a0, 8
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; ZVFBFMIN-NEXT: addi a1, a0, -1
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; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; ZVFBFMIN-NEXT: vand.vx v8, v8, a1
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; ZVFBFMIN-NEXT: addi a0, a0, -128
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; ZVFBFMIN-NEXT: vmsgt.vx v0, v8, a0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: isnan_v8bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: li a0, 768
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; ZVFBFA-NEXT: vand.vx v8, v8, a0
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; ZVFBFA-NEXT: vmsne.vi v0, v8, 0
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; ZVFBFA-NEXT: ret
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%1 = call <8 x i1> @llvm.is.fpclass.v8bf16(<8 x bfloat> %x, i32 3) ; nan
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ret <8 x i1> %1
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}
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define <16 x i1> @isnan_v16bf16(<16 x bfloat> %x) {
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; ZVFBFMIN-LABEL: isnan_v16bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: lui a0, 8
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; ZVFBFMIN-NEXT: addi a1, a0, -1
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; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; ZVFBFMIN-NEXT: vand.vx v8, v8, a1
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; ZVFBFMIN-NEXT: addi a0, a0, -128
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; ZVFBFMIN-NEXT: vmsgt.vx v0, v8, a0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: isnan_v16bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: li a0, 768
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; ZVFBFA-NEXT: vand.vx v8, v8, a0
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; ZVFBFA-NEXT: vmsne.vi v0, v8, 0
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; ZVFBFA-NEXT: ret
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%1 = call <16 x i1> @llvm.is.fpclass.v16bf16(<16 x bfloat> %x, i32 3) ; nan
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ret <16 x i1> %1
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}
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define <4 x i1> @isinf_v4bf16(<4 x bfloat> %x) {
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; ZVFBFMIN-LABEL: isinf_v4bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: lui a0, 8
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; ZVFBFMIN-NEXT: addi a1, a0, -1
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; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFBFMIN-NEXT: vand.vx v8, v8, a1
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; ZVFBFMIN-NEXT: addi a0, a0, -128
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; ZVFBFMIN-NEXT: vmseq.vx v0, v8, a0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: isinf_v4bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: li a0, 129
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; ZVFBFA-NEXT: vand.vx v8, v8, a0
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; ZVFBFA-NEXT: vmsne.vi v0, v8, 0
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; ZVFBFA-NEXT: ret
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%1 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> %x, i32 516) ; inf
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ret <4 x i1> %1
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}
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define <8 x i1> @iszero_v8bf16(<8 x bfloat> %x) {
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; ZVFBFMIN-LABEL: iszero_v8bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: lui a0, 8
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; ZVFBFMIN-NEXT: addi a0, a0, -1
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; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
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; ZVFBFMIN-NEXT: vmseq.vi v0, v8, 0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: iszero_v8bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: li a0, 24
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; ZVFBFA-NEXT: vand.vx v8, v8, a0
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; ZVFBFA-NEXT: vmsne.vi v0, v8, 0
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; ZVFBFA-NEXT: ret
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%1 = call <8 x i1> @llvm.is.fpclass.v8bf16(<8 x bfloat> %x, i32 96) ; zero
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ret <8 x i1> %1
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}
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define <8 x i1> @isfinite_v8bf16(<8 x bfloat> %x) {
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; ZVFBFMIN-LABEL: isfinite_v8bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; ZVFBFMIN-NEXT: vadd.vv v8, v8, v8
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; ZVFBFMIN-NEXT: li a0, -256
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; ZVFBFMIN-NEXT: vmsltu.vx v0, v8, a0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: isfinite_v8bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: li a0, 126
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; ZVFBFA-NEXT: vand.vx v8, v8, a0
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; ZVFBFA-NEXT: vmsne.vi v0, v8, 0
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; ZVFBFA-NEXT: ret
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%1 = call <8 x i1> @llvm.is.fpclass.v8bf16(<8 x bfloat> %x, i32 504) ; finite
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ret <8 x i1> %1
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}
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define <4 x i1> @isposinf_v4bf16(<4 x bfloat> %x) {
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; ZVFBFMIN-LABEL: isposinf_v4bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: lui a0, 8
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; ZVFBFMIN-NEXT: addi a0, a0, -128
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; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFBFMIN-NEXT: vmseq.vx v0, v8, a0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: isposinf_v4bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: li a0, 128
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; ZVFBFA-NEXT: vmseq.vx v0, v8, a0
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; ZVFBFA-NEXT: ret
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%1 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> %x, i32 512) ; +inf
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ret <4 x i1> %1
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}
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define <4 x i1> @isneginf_v4bf16(<4 x bfloat> %x) {
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; ZVFBFMIN-LABEL: isneginf_v4bf16:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: li a0, -128
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; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFBFMIN-NEXT: vmseq.vx v0, v8, a0
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: isneginf_v4bf16:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
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; ZVFBFA-NEXT: vfclass.v v8, v8
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; ZVFBFA-NEXT: vmseq.vi v0, v8, 1
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; ZVFBFA-NEXT: ret
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%1 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> %x, i32 4) ; -inf
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ret <4 x i1> %1
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}
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define <2 x i1> @isnan_v2f16(<2 x half> %x) {
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; CHECK-LABEL: isnan_v2f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 768
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 3) ; nan
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ret <2 x i1> %1
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}
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define <2 x i1> @isnan_v2f32(<2 x float> %x) {
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; CHECK-LABEL: isnan_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 927
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 639)
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ret <2 x i1> %1
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}
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define <4 x i1> @isnan_v4f32(<4 x float> %x) {
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; CHECK-LABEL: isnan_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 768
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) ; nan
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ret <4 x i1> %1
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}
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define <8 x i1> @isnan_v8f32(<8 x float> %x) {
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; CHECK-LABEL: isnan_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 512
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%1 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> %x, i32 2)
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ret <8 x i1> %1
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}
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define <16 x i1> @isnan_v16f32(<16 x float> %x) {
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; CHECK-LABEL: isnan_v16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 256
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%1 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> %x, i32 1)
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ret <16 x i1> %1
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}
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define <2 x i1> @isnormal_v2f64(<2 x double> %x) {
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; CHECK-LABEL: isnormal_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 129
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> %x, i32 516) ; 0x204 = "inf"
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ret <2 x i1> %1
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}
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define <4 x i1> @isposinf_v4f64(<4 x double> %x) {
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; CHECK-LABEL: isposinf_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 128
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%1 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> %x, i32 512) ; 0x200 = "+inf"
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ret <4 x i1> %1
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}
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define <8 x i1> @isneginf_v8f64(<8 x double> %x) {
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; CHECK-LABEL: isneginf_v8f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: vmseq.vi v0, v8, 1
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; CHECK-NEXT: ret
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%1 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> %x, i32 4) ; "-inf"
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ret <8 x i1> %1
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}
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define <16 x i1> @isfinite_v16f64(<16 x double> %x) {
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; CHECK-LABEL: isfinite_v16f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 126
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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|
; CHECK-NEXT: ret
|
|
%1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 504) ; 0x1f8 = "finite"
|
|
ret <16 x i1> %1
|
|
}
|
|
|
|
define <16 x i1> @isposfinite_v16f64(<16 x double> %x) {
|
|
; CHECK-LABEL: isposfinite_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfclass.v v8, v8
|
|
; CHECK-NEXT: li a0, 112
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: vmsne.vi v0, v8, 0
|
|
; CHECK-NEXT: ret
|
|
%1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 448) ; 0x1c0 = "+finite"
|
|
ret <16 x i1> %1
|
|
}
|
|
|
|
define <16 x i1> @isnegfinite_v16f64(<16 x double> %x) {
|
|
; CHECK-LABEL: isnegfinite_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfclass.v v8, v8
|
|
; CHECK-NEXT: vand.vi v8, v8, 14
|
|
; CHECK-NEXT: vmsne.vi v0, v8, 0
|
|
; CHECK-NEXT: ret
|
|
%1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 56) ; 0x38 = "-finite"
|
|
ret <16 x i1> %1
|
|
}
|
|
|
|
define <16 x i1> @isnotfinite_v16f64(<16 x double> %x) {
|
|
; CHECK-LABEL: isnotfinite_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfclass.v v8, v8
|
|
; CHECK-NEXT: li a0, 897
|
|
; CHECK-NEXT: vand.vx v8, v8, a0
|
|
; CHECK-NEXT: vmsne.vi v0, v8, 0
|
|
; CHECK-NEXT: ret
|
|
%1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 519) ; 0x207 = "inf|nan"
|
|
ret <16 x i1> %1
|
|
}
|
|
|