derek.holloway
7502bf64a4
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396 lines
14 KiB
LLVM
396 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <2 x i8> @vpload_v2i8(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <2 x i8> @llvm.vp.load.v2i8.p0(ptr %ptr, <2 x i1> %m, i32 %evl)
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ret <2 x i8> %load
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}
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define <3 x i8> @vpload_v3i8(ptr %ptr, <3 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v3i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <3 x i8> @llvm.vp.load.v3i8.p0(ptr %ptr, <3 x i1> %m, i32 %evl)
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ret <3 x i8> %load
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}
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define <4 x i8> @vpload_v4i8(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <4 x i8> @llvm.vp.load.v4i8.p0(ptr %ptr, <4 x i1> %m, i32 %evl)
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ret <4 x i8> %load
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}
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define <4 x i8> @vpload_v4i8_allones_mask(ptr %ptr, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4i8_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: ret
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%load = call <4 x i8> @llvm.vp.load.v4i8.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x i8> %load
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}
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define <8 x i8> @vpload_v8i8(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <8 x i8> @llvm.vp.load.v8i8.p0(ptr %ptr, <8 x i1> %m, i32 %evl)
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ret <8 x i8> %load
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}
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define <2 x i16> @vpload_v2i16(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <2 x i16> @llvm.vp.load.v2i16.p0(ptr %ptr, <2 x i1> %m, i32 %evl)
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ret <2 x i16> %load
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}
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define <4 x i16> @vpload_v4i16(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <4 x i16> @llvm.vp.load.v4i16.p0(ptr %ptr, <4 x i1> %m, i32 %evl)
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ret <4 x i16> %load
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}
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define <8 x i16> @vpload_v8i16(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <8 x i16> @llvm.vp.load.v8i16.p0(ptr %ptr, <8 x i1> %m, i32 %evl)
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ret <8 x i16> %load
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}
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define <8 x i16> @vpload_v8i16_allones_mask(ptr %ptr, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8i16_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: ret
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%load = call <8 x i16> @llvm.vp.load.v8i16.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)
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ret <8 x i16> %load
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}
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define <2 x i32> @vpload_v2i32(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <2 x i32> @llvm.vp.load.v2i32.p0(ptr %ptr, <2 x i1> %m, i32 %evl)
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ret <2 x i32> %load
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}
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define <4 x i32> @vpload_v4i32(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <4 x i32> @llvm.vp.load.v4i32.p0(ptr %ptr, <4 x i1> %m, i32 %evl)
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ret <4 x i32> %load
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}
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define <6 x i32> @vpload_v6i32(ptr %ptr, <6 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v6i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <6 x i32> @llvm.vp.load.v6i32.p0(ptr %ptr, <6 x i1> %m, i32 %evl)
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ret <6 x i32> %load
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}
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define <6 x i32> @vpload_v6i32_allones_mask(ptr %ptr, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v6i32_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: ret
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%load = call <6 x i32> @llvm.vp.load.v6i32.p0(ptr %ptr, <6 x i1> splat (i1 true), i32 %evl)
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ret <6 x i32> %load
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}
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define <8 x i32> @vpload_v8i32(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> %m, i32 %evl)
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ret <8 x i32> %load
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}
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define <8 x i32> @vpload_v8i32_allones_mask(ptr %ptr, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8i32_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: ret
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%load = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)
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ret <8 x i32> %load
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}
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define <2 x i64> @vpload_v2i64(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
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; CHECK-NEXT: vle64.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <2 x i64> @llvm.vp.load.v2i64.p0(ptr %ptr, <2 x i1> %m, i32 %evl)
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ret <2 x i64> %load
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}
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define <4 x i64> @vpload_v4i64(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
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; CHECK-NEXT: vle64.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <4 x i64> @llvm.vp.load.v4i64.p0(ptr %ptr, <4 x i1> %m, i32 %evl)
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ret <4 x i64> %load
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}
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define <4 x i64> @vpload_v4i64_allones_mask(ptr %ptr, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4i64_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
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; CHECK-NEXT: vle64.v v8, (a0)
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; CHECK-NEXT: ret
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%load = call <4 x i64> @llvm.vp.load.v4i64.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x i64> %load
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}
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define <8 x i64> @vpload_v8i64(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vle64.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <8 x i64> @llvm.vp.load.v8i64.p0(ptr %ptr, <8 x i1> %m, i32 %evl)
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ret <8 x i64> %load
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}
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define <2 x half> @vpload_v2f16(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v2f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <2 x half> @llvm.vp.load.v2f16.p0(ptr %ptr, <2 x i1> %m, i32 %evl)
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ret <2 x half> %load
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}
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define <2 x half> @vpload_v2f16_allones_mask(ptr %ptr, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v2f16_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: ret
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%load = call <2 x half> @llvm.vp.load.v2f16.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)
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ret <2 x half> %load
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}
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define <4 x half> @vpload_v4f16(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <4 x half> @llvm.vp.load.v4f16.p0(ptr %ptr, <4 x i1> %m, i32 %evl)
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ret <4 x half> %load
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}
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define <8 x half> @vpload_v8f16(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <8 x half> @llvm.vp.load.v8f16.p0(ptr %ptr, <8 x i1> %m, i32 %evl)
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ret <8 x half> %load
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}
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define <2 x float> @vpload_v2f32(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <2 x float> @llvm.vp.load.v2f32.p0(ptr %ptr, <2 x i1> %m, i32 %evl)
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ret <2 x float> %load
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}
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define <4 x float> @vpload_v4f32(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <4 x float> @llvm.vp.load.v4f32.p0(ptr %ptr, <4 x i1> %m, i32 %evl)
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ret <4 x float> %load
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}
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define <8 x float> @vpload_v8f32(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <8 x float> @llvm.vp.load.v8f32.p0(ptr %ptr, <8 x i1> %m, i32 %evl)
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ret <8 x float> %load
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}
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define <8 x float> @vpload_v8f32_allones_mask(ptr %ptr, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v8f32_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: ret
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%load = call <8 x float> @llvm.vp.load.v8f32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)
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ret <8 x float> %load
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}
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define <2 x double> @vpload_v2f64(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
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; CHECK-NEXT: vle64.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <2 x double> @llvm.vp.load.v2f64.p0(ptr %ptr, <2 x i1> %m, i32 %evl)
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ret <2 x double> %load
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}
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define <4 x double> @vpload_v4f64(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
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; CHECK-NEXT: vle64.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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%load = call <4 x double> @llvm.vp.load.v4f64.p0(ptr %ptr, <4 x i1> %m, i32 %evl)
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ret <4 x double> %load
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}
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define <4 x double> @vpload_v4f64_allones_mask(ptr %ptr, i32 zeroext %evl) {
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; CHECK-LABEL: vpload_v4f64_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
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; CHECK-NEXT: vle64.v v8, (a0)
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; CHECK-NEXT: ret
|
|
%load = call <4 x double> @llvm.vp.load.v4f64.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x double> %load
|
|
}
|
|
|
|
define <8 x double> @vpload_v8f64(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vpload_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0), v0.t
|
|
; CHECK-NEXT: ret
|
|
%load = call <8 x double> @llvm.vp.load.v8f64.p0(ptr %ptr, <8 x i1> %m, i32 %evl)
|
|
ret <8 x double> %load
|
|
}
|
|
|
|
define <32 x double> @vpload_v32f64(ptr %ptr, <32 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vpload_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a3, 16
|
|
; CHECK-NEXT: mv a2, a1
|
|
; CHECK-NEXT: bltu a1, a3, .LBB31_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: li a2, 16
|
|
; CHECK-NEXT: .LBB31_2:
|
|
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0), v0.t
|
|
; CHECK-NEXT: addi a2, a1, -16
|
|
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
|
|
; CHECK-NEXT: vslidedown.vi v0, v0, 2
|
|
; CHECK-NEXT: sltu a1, a1, a2
|
|
; CHECK-NEXT: addi a1, a1, -1
|
|
; CHECK-NEXT: and a1, a1, a2
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v16, (a0), v0.t
|
|
; CHECK-NEXT: ret
|
|
%load = call <32 x double> @llvm.vp.load.v32f64.p0(ptr %ptr, <32 x i1> %m, i32 %evl)
|
|
ret <32 x double> %load
|
|
}
|
|
|
|
; Widen to v64f64 then split into 4 x v16f64, of which 1 is empty.
|
|
|
|
define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vpload_v33f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
|
|
; CHECK-NEXT: vmv1r.v v8, v0
|
|
; CHECK-NEXT: li a4, 32
|
|
; CHECK-NEXT: mv a3, a2
|
|
; CHECK-NEXT: bltu a2, a4, .LBB32_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: li a3, 32
|
|
; CHECK-NEXT: .LBB32_2:
|
|
; CHECK-NEXT: addi a5, a3, -16
|
|
; CHECK-NEXT: addi a4, a1, 128
|
|
; CHECK-NEXT: addi a7, a2, -32
|
|
; CHECK-NEXT: sltu a3, a3, a5
|
|
; CHECK-NEXT: addi a3, a3, -1
|
|
; CHECK-NEXT: and a6, a3, a5
|
|
; CHECK-NEXT: sltu a3, a2, a7
|
|
; CHECK-NEXT: addi a3, a3, -1
|
|
; CHECK-NEXT: and a5, a3, a7
|
|
; CHECK-NEXT: li a3, 16
|
|
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
|
|
; CHECK-NEXT: vslidedown.vi v0, v8, 2
|
|
; CHECK-NEXT: bltu a5, a3, .LBB32_4
|
|
; CHECK-NEXT: # %bb.3:
|
|
; CHECK-NEXT: li a5, 16
|
|
; CHECK-NEXT: .LBB32_4:
|
|
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v16, (a4), v0.t
|
|
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vslidedown.vi v0, v8, 4
|
|
; CHECK-NEXT: addi a4, a1, 256
|
|
; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v24, (a4), v0.t
|
|
; CHECK-NEXT: bltu a2, a3, .LBB32_6
|
|
; CHECK-NEXT: # %bb.5:
|
|
; CHECK-NEXT: li a2, 16
|
|
; CHECK-NEXT: .LBB32_6:
|
|
; CHECK-NEXT: vmv1r.v v0, v8
|
|
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a1), v0.t
|
|
; CHECK-NEXT: addi a1, a0, 128
|
|
; CHECK-NEXT: addi a2, a0, 256
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vse64.v v8, (a0)
|
|
; CHECK-NEXT: vse64.v v16, (a1)
|
|
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
|
|
; CHECK-NEXT: vse64.v v24, (a2)
|
|
; CHECK-NEXT: ret
|
|
%load = call <33 x double> @llvm.vp.load.v33f64.p0(ptr %ptr, <33 x i1> %m, i32 %evl)
|
|
ret <33 x double> %load
|
|
}
|