derek.holloway
7502bf64a4
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1057 lines
41 KiB
LLVM
1057 lines
41 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
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define <8 x i7> @vsra_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v8i7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 127
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: vsra.vi v8, v8, 1
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <8 x i7> @llvm.vp.ashr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
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ret <8 x i7> %v
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}
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define <2 x i8> @vsra_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vsra_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v2i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vsra_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vx_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vsra.vx v8, v8, a0
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; CHECK-NEXT: ret
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%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
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%vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
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%v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vsra_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vx_v2i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vsra.vx v8, v8, a0
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; CHECK-NEXT: ret
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%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
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%vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
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%v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vsra_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vi_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vsra.vi v8, v8, 5
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> %m, i32 %evl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vsra_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vi_v2i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vsra.vi v8, v8, 5
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> splat (i1 true), i32 %evl)
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ret <2 x i8> %v
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}
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define <4 x i8> @vsra_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
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ret <4 x i8> %v
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}
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define <4 x i8> @vsra_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v4i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x i8> %v
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}
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define <4 x i8> @vsra_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vx_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vsra.vx v8, v8, a0
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; CHECK-NEXT: ret
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%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
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%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
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%v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
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ret <4 x i8> %v
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}
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define <4 x i8> @vsra_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vx_v4i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vsra.vx v8, v8, a0
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; CHECK-NEXT: ret
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%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
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%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
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%v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x i8> %v
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}
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define <4 x i8> @vsra_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vi_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vsra.vi v8, v8, 5
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> %m, i32 %evl)
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ret <4 x i8> %v
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}
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define <4 x i8> @vsra_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vi_v4i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vsra.vi v8, v8, 5
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> splat (i1 true), i32 %evl)
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ret <4 x i8> %v
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}
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define <7 x i8> @vsra_vv_v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v7i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <7 x i8> @llvm.vp.ashr.v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> %m, i32 %evl)
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ret <7 x i8> %v
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}
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define <8 x i8> @vsra_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
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ret <8 x i8> %v
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}
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define <8 x i8> @vsra_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v8i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
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ret <8 x i8> %v
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}
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define <8 x i8> @vsra_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vx_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsra.vx v8, v8, a0
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; CHECK-NEXT: ret
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%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
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%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
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%v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
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ret <8 x i8> %v
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}
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define <8 x i8> @vsra_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vx_v8i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsra.vx v8, v8, a0
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; CHECK-NEXT: ret
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%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
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%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
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%v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
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ret <8 x i8> %v
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}
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define <8 x i8> @vsra_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vi_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsra.vi v8, v8, 5
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> %m, i32 %evl)
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ret <8 x i8> %v
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}
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define <8 x i8> @vsra_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vi_v8i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vsra.vi v8, v8, 5
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> splat (i1 true), i32 %evl)
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ret <8 x i8> %v
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}
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define <16 x i8> @vsra_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
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ret <16 x i8> %v
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}
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define <16 x i8> @vsra_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
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; CHECK-LABEL: vsra_vv_v16i8_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vsra.vv v8, v8, v9
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; CHECK-NEXT: ret
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%v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
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ret <16 x i8> %v
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}
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define <16 x i8> @vsra_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vsra.vx v8, v8, a0
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; CHECK-NEXT: ret
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%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
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%vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
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%v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
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ret <16 x i8> %v
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}
|
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|
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define <16 x i8> @vsra_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v16i8_unmasked:
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|
; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
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%vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
|
|
%v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
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ret <16 x i8> %v
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}
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define <16 x i8> @vsra_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v16i8:
|
|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> %m, i32 %evl)
|
|
ret <16 x i8> %v
|
|
}
|
|
|
|
define <16 x i8> @vsra_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v16i8_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i8> %v
|
|
}
|
|
|
|
define <2 x i16> @vsra_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v2i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
|
|
ret <2 x i16> %v
|
|
}
|
|
|
|
define <2 x i16> @vsra_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v2i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i16> %v
|
|
}
|
|
|
|
define <2 x i16> @vsra_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v2i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
|
|
%vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
|
|
%v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
|
|
ret <2 x i16> %v
|
|
}
|
|
|
|
define <2 x i16> @vsra_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v2i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
|
|
%vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
|
|
%v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i16> %v
|
|
}
|
|
|
|
define <2 x i16> @vsra_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v2i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> %m, i32 %evl)
|
|
ret <2 x i16> %v
|
|
}
|
|
|
|
define <2 x i16> @vsra_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v2i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i16> %v
|
|
}
|
|
|
|
define <4 x i16> @vsra_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v4i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
|
|
ret <4 x i16> %v
|
|
}
|
|
|
|
define <4 x i16> @vsra_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v4i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i16> %v
|
|
}
|
|
|
|
define <4 x i16> @vsra_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v4i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
|
|
%vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
|
|
%v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
|
|
ret <4 x i16> %v
|
|
}
|
|
|
|
define <4 x i16> @vsra_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v4i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
|
|
%vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
|
|
%v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i16> %v
|
|
}
|
|
|
|
define <4 x i16> @vsra_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v4i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> %m, i32 %evl)
|
|
ret <4 x i16> %v
|
|
}
|
|
|
|
define <4 x i16> @vsra_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v4i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i16> %v
|
|
}
|
|
|
|
define <8 x i16> @vsra_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i16> %v
|
|
}
|
|
|
|
define <8 x i16> @vsra_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v8i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i16> %v
|
|
}
|
|
|
|
define <8 x i16> @vsra_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
|
|
%vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
|
|
%v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i16> %v
|
|
}
|
|
|
|
define <8 x i16> @vsra_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v8i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
|
|
%vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
|
|
%v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i16> %v
|
|
}
|
|
|
|
define <8 x i16> @vsra_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> %m, i32 %evl)
|
|
ret <8 x i16> %v
|
|
}
|
|
|
|
define <8 x i16> @vsra_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v8i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i16> %v
|
|
}
|
|
|
|
define <16 x i16> @vsra_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v16i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i16> %v
|
|
}
|
|
|
|
define <16 x i16> @vsra_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v16i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i16> %v
|
|
}
|
|
|
|
define <16 x i16> @vsra_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v16i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
|
|
%vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
|
|
%v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i16> %v
|
|
}
|
|
|
|
define <16 x i16> @vsra_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v16i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
|
|
%vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
|
|
%v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i16> %v
|
|
}
|
|
|
|
define <16 x i16> @vsra_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v16i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> %m, i32 %evl)
|
|
ret <16 x i16> %v
|
|
}
|
|
|
|
define <16 x i16> @vsra_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v16i16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i16> %v
|
|
}
|
|
|
|
define <2 x i32> @vsra_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v2i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
|
|
ret <2 x i32> %v
|
|
}
|
|
|
|
define <2 x i32> @vsra_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v2i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i32> %v
|
|
}
|
|
|
|
define <2 x i32> @vsra_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v2i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
|
|
%vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
|
|
%v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
|
|
ret <2 x i32> %v
|
|
}
|
|
|
|
define <2 x i32> @vsra_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v2i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
|
|
%vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
|
|
%v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i32> %v
|
|
}
|
|
|
|
define <2 x i32> @vsra_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v2i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> %m, i32 %evl)
|
|
ret <2 x i32> %v
|
|
}
|
|
|
|
define <2 x i32> @vsra_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v2i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i32> %v
|
|
}
|
|
|
|
define <4 x i32> @vsra_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
|
|
ret <4 x i32> %v
|
|
}
|
|
|
|
define <4 x i32> @vsra_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v4i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i32> %v
|
|
}
|
|
|
|
define <4 x i32> @vsra_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
|
|
%vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
|
|
%v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
|
|
ret <4 x i32> %v
|
|
}
|
|
|
|
define <4 x i32> @vsra_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v4i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
|
|
%vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
|
|
%v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i32> %v
|
|
}
|
|
|
|
define <4 x i32> @vsra_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> %m, i32 %evl)
|
|
ret <4 x i32> %v
|
|
}
|
|
|
|
define <4 x i32> @vsra_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v4i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i32> %v
|
|
}
|
|
|
|
define <8 x i32> @vsra_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v8i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i32> %v
|
|
}
|
|
|
|
define <8 x i32> @vsra_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v8i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i32> %v
|
|
}
|
|
|
|
define <8 x i32> @vsra_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v8i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
|
|
%vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
|
|
%v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i32> %v
|
|
}
|
|
|
|
define <8 x i32> @vsra_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v8i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
|
|
%vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
|
|
%v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i32> %v
|
|
}
|
|
|
|
define <8 x i32> @vsra_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v8i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> %m, i32 %evl)
|
|
ret <8 x i32> %v
|
|
}
|
|
|
|
define <8 x i32> @vsra_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v8i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i32> %v
|
|
}
|
|
|
|
define <16 x i32> @vsra_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v16i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i32> %v
|
|
}
|
|
|
|
define <16 x i32> @vsra_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v16i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i32> %v
|
|
}
|
|
|
|
define <16 x i32> @vsra_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v16i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
|
|
%vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
|
|
%v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i32> %v
|
|
}
|
|
|
|
define <16 x i32> @vsra_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v16i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
|
|
%vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
|
|
%v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i32> %v
|
|
}
|
|
|
|
define <16 x i32> @vsra_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v16i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> %m, i32 %evl)
|
|
ret <16 x i32> %v
|
|
}
|
|
|
|
define <16 x i32> @vsra_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v16i32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i32> %v
|
|
}
|
|
|
|
define <2 x i64> @vsra_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
|
|
ret <2 x i64> %v
|
|
}
|
|
|
|
define <2 x i64> @vsra_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v2i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v9
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i64> %v
|
|
}
|
|
|
|
define <2 x i64> @vsra_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
|
|
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
|
|
%v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
|
|
ret <2 x i64> %v
|
|
}
|
|
|
|
define <2 x i64> @vsra_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v2i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
|
|
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
|
|
%v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i64> %v
|
|
}
|
|
|
|
define <2 x i64> @vsra_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> %m, i32 %evl)
|
|
ret <2 x i64> %v
|
|
}
|
|
|
|
define <2 x i64> @vsra_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v2i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> splat (i1 true), i32 %evl)
|
|
ret <2 x i64> %v
|
|
}
|
|
|
|
define <4 x i64> @vsra_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v4i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
|
|
ret <4 x i64> %v
|
|
}
|
|
|
|
define <4 x i64> @vsra_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v4i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i64> %v
|
|
}
|
|
|
|
define <4 x i64> @vsra_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v4i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
|
|
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
|
|
%v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
|
|
ret <4 x i64> %v
|
|
}
|
|
|
|
define <4 x i64> @vsra_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v4i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
|
|
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
|
|
%v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i64> %v
|
|
}
|
|
|
|
define <4 x i64> @vsra_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v4i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> %m, i32 %evl)
|
|
ret <4 x i64> %v
|
|
}
|
|
|
|
define <4 x i64> @vsra_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v4i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> splat (i1 true), i32 %evl)
|
|
ret <4 x i64> %v
|
|
}
|
|
|
|
define <8 x i64> @vsra_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v8i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i64> %v
|
|
}
|
|
|
|
define <8 x i64> @vsra_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v8i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i64> %v
|
|
}
|
|
|
|
define <8 x i64> @vsra_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v8i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
|
|
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
|
|
%v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
|
|
ret <8 x i64> %v
|
|
}
|
|
|
|
define <8 x i64> @vsra_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v8i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
|
|
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
|
|
%v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i64> %v
|
|
}
|
|
|
|
define <8 x i64> @vsra_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v8i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> %m, i32 %evl)
|
|
ret <8 x i64> %v
|
|
}
|
|
|
|
define <8 x i64> @vsra_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v8i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> splat (i1 true), i32 %evl)
|
|
ret <8 x i64> %v
|
|
}
|
|
|
|
define <16 x i64> @vsra_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v16i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i64> %v
|
|
}
|
|
|
|
define <16 x i64> @vsra_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vv_v16i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vsra.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i64> %v
|
|
}
|
|
|
|
define <16 x i64> @vsra_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v16i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
|
|
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
|
|
%v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
|
|
ret <16 x i64> %v
|
|
}
|
|
|
|
define <16 x i64> @vsra_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vx_v16i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vsra.vx v8, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
|
|
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
|
|
%v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i64> %v
|
|
}
|
|
|
|
define <16 x i64> @vsra_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v16i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> %m, i32 %evl)
|
|
ret <16 x i64> %v
|
|
}
|
|
|
|
define <16 x i64> @vsra_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vsra_vi_v16i64_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vsra.vi v8, v8, 5
|
|
; CHECK-NEXT: ret
|
|
%v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> splat (i1 true), i32 %evl)
|
|
ret <16 x i64> %v
|
|
}
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
|
; RV32: {{.*}}
|
|
; RV64: {{.*}}
|