derek.holloway
7502bf64a4
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1878 lines
75 KiB
LLVM
1878 lines
75 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \
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; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH,RV32ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH,RV64ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
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; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN
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define <vscale x 1 x bfloat> @vp_floor_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vfabs.v v8, v9
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x bfloat> @llvm.vp.floor.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
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ret <vscale x 1 x bfloat> %v
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}
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define <vscale x 1 x bfloat> @vp_floor_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv1bf16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vfabs.v v8, v9
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x bfloat> @llvm.vp.floor.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 1 x bfloat> %v
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}
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define <vscale x 2 x bfloat> @vp_floor_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vfabs.v v8, v9
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
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; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x bfloat> @llvm.vp.floor.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
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ret <vscale x 2 x bfloat> %v
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}
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define <vscale x 2 x bfloat> @vp_floor_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv2bf16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vfabs.v v8, v9
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
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; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x bfloat> @llvm.vp.floor.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 2 x bfloat> %v
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}
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define <vscale x 4 x bfloat> @vp_floor_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfabs.v v8, v10
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
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; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x bfloat> @llvm.vp.floor.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 %evl)
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ret <vscale x 4 x bfloat> %v
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}
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define <vscale x 4 x bfloat> @vp_floor_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv4bf16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfabs.v v8, v10
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
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; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x bfloat> @llvm.vp.floor.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 4 x bfloat> %v
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}
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define <vscale x 8 x bfloat> @vp_floor_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vfabs.v v8, v12
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
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; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x bfloat> @llvm.vp.floor.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 %evl)
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ret <vscale x 8 x bfloat> %v
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}
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define <vscale x 8 x bfloat> @vp_floor_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv8bf16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vfabs.v v8, v12
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
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; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x bfloat> @llvm.vp.floor.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 8 x bfloat> %v
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}
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define <vscale x 16 x bfloat> @vp_floor_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfabs.v v8, v16
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
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; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x bfloat> @llvm.vp.floor.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 %evl)
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ret <vscale x 16 x bfloat> %v
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}
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define <vscale x 16 x bfloat> @vp_floor_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv16bf16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfabs.v v8, v16
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
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; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x bfloat> @llvm.vp.floor.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 16 x bfloat> %v
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}
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define <vscale x 32 x bfloat> @vp_floor_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_floor_nxv32bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
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; CHECK-NEXT: lui a0, 307200
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfabs.v v24, v16
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: vmflt.vf v0, v24, fa5
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; CHECK-NEXT: fsrmi a0, 2
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; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
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; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfabs.v v8, v24
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; CHECK-NEXT: vmflt.vf v0, v8, fa5
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 32 x bfloat> @llvm.vp.floor.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
|
|
ret <vscale x 32 x bfloat> %v
|
|
}
|
|
|
|
define <vscale x 32 x bfloat> @vp_floor_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv32bf16_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfabs.v v24, v16
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v24, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfabs.v v8, v24
|
|
; CHECK-NEXT: vmflt.vf v0, v8, fa5
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 32 x bfloat> @llvm.vp.floor.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 32 x bfloat> %v
|
|
}
|
|
|
|
define <vscale x 1 x half> @vp_floor_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv1f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v9, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv1f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v9
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 1 x half> @llvm.vp.floor.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
|
|
ret <vscale x 1 x half> %v
|
|
}
|
|
|
|
define <vscale x 1 x half> @vp_floor_nxv1f16_unmasked(<vscale x 1 x half> %va, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv1f16_unmasked:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v9, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv1f16_unmasked:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v9
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 1 x half> @llvm.vp.floor.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 1 x half> %v
|
|
}
|
|
|
|
define <vscale x 2 x half> @vp_floor_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv2f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v9, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv2f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v9
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 2 x half> @llvm.vp.floor.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
|
|
ret <vscale x 2 x half> %v
|
|
}
|
|
|
|
define <vscale x 2 x half> @vp_floor_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv2f16_unmasked:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v9, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv2f16_unmasked:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v9
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 2 x half> @llvm.vp.floor.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 2 x half> %v
|
|
}
|
|
|
|
define <vscale x 4 x half> @vp_floor_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv4f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v9, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv4f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v10
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 4 x half> @llvm.vp.floor.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 %evl)
|
|
ret <vscale x 4 x half> %v
|
|
}
|
|
|
|
define <vscale x 4 x half> @vp_floor_nxv4f16_unmasked(<vscale x 4 x half> %va, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv4f16_unmasked:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v9, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv4f16_unmasked:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v10
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 4 x half> @llvm.vp.floor.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 4 x half> %v
|
|
}
|
|
|
|
define <vscale x 8 x half> @vp_floor_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv8f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v10, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv8f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v12
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 8 x half> @llvm.vp.floor.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 %evl)
|
|
ret <vscale x 8 x half> %v
|
|
}
|
|
|
|
define <vscale x 8 x half> @vp_floor_nxv8f16_unmasked(<vscale x 8 x half> %va, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv8f16_unmasked:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v10, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v10, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv8f16_unmasked:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v12
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 8 x half> @llvm.vp.floor.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 8 x half> %v
|
|
}
|
|
|
|
define <vscale x 16 x half> @vp_floor_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv16f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v12, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv16f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v16
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 16 x half> @llvm.vp.floor.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 %evl)
|
|
ret <vscale x 16 x half> %v
|
|
}
|
|
|
|
define <vscale x 16 x half> @vp_floor_nxv16f16_unmasked(<vscale x 16 x half> %va, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv16f16_unmasked:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v12, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv16f16_unmasked:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v16
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 16 x half> @llvm.vp.floor.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 16 x half> %v
|
|
}
|
|
|
|
define <vscale x 32 x half> @vp_floor_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv32f16:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v16, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv32f16:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v24, v16
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v24
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 32 x half> @llvm.vp.floor.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
|
|
ret <vscale x 32 x half> %v
|
|
}
|
|
|
|
define <vscale x 32 x half> @vp_floor_nxv32f16_unmasked(<vscale x 32 x half> %va, i32 zeroext %evl) {
|
|
; ZVFH-LABEL: vp_floor_nxv32f16_unmasked:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vfabs.v v16, v8
|
|
; ZVFH-NEXT: li a0, 25
|
|
; ZVFH-NEXT: slli a0, a0, 10
|
|
; ZVFH-NEXT: fmv.h.x fa5, a0
|
|
; ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; ZVFH-NEXT: fsrmi a0, 2
|
|
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; ZVFH-NEXT: fsrm a0
|
|
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu
|
|
; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vp_floor_nxv32f16_unmasked:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
|
|
; ZVFHMIN-NEXT: lui a0, 307200
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v24, v16
|
|
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfabs.v v8, v24
|
|
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
|
|
; ZVFHMIN-NEXT: fsrm a0
|
|
; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 32 x half> @llvm.vp.floor.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 32 x half> %v
|
|
}
|
|
|
|
define <vscale x 1 x float> @vp_floor_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv1f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfabs.v v9, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v9, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 1 x float> @llvm.vp.floor.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 %evl)
|
|
ret <vscale x 1 x float> %v
|
|
}
|
|
|
|
define <vscale x 1 x float> @vp_floor_nxv1f32_unmasked(<vscale x 1 x float> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv1f32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfabs.v v9, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v9, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 1 x float> @llvm.vp.floor.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 1 x float> %v
|
|
}
|
|
|
|
define <vscale x 2 x float> @vp_floor_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfabs.v v9, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v9, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 2 x float> @llvm.vp.floor.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)
|
|
ret <vscale x 2 x float> %v
|
|
}
|
|
|
|
define <vscale x 2 x float> @vp_floor_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv2f32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfabs.v v9, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v9, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 2 x float> @llvm.vp.floor.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 2 x float> %v
|
|
}
|
|
|
|
define <vscale x 4 x float> @vp_floor_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfabs.v v10, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v10, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 4 x float> @llvm.vp.floor.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)
|
|
ret <vscale x 4 x float> %v
|
|
}
|
|
|
|
define <vscale x 4 x float> @vp_floor_nxv4f32_unmasked(<vscale x 4 x float> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv4f32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfabs.v v10, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v10, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 4 x float> @llvm.vp.floor.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 4 x float> %v
|
|
}
|
|
|
|
define <vscale x 8 x float> @vp_floor_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfabs.v v12, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v12, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 8 x float> @llvm.vp.floor.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)
|
|
ret <vscale x 8 x float> %v
|
|
}
|
|
|
|
define <vscale x 8 x float> @vp_floor_nxv8f32_unmasked(<vscale x 8 x float> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv8f32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfabs.v v12, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v12, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 8 x float> @llvm.vp.floor.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 8 x float> %v
|
|
}
|
|
|
|
define <vscale x 16 x float> @vp_floor_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfabs.v v16, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v16, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x float> @llvm.vp.floor.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)
|
|
ret <vscale x 16 x float> %v
|
|
}
|
|
|
|
define <vscale x 16 x float> @vp_floor_nxv16f32_unmasked(<vscale x 16 x float> %va, i32 zeroext %evl) {
|
|
; CHECK-LABEL: vp_floor_nxv16f32_unmasked:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfabs.v v16, v8
|
|
; CHECK-NEXT: lui a0, 307200
|
|
; CHECK-NEXT: fmv.w.x fa5, a0
|
|
; CHECK-NEXT: vmflt.vf v0, v16, fa5
|
|
; CHECK-NEXT: fsrmi a0, 2
|
|
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; CHECK-NEXT: fsrm a0
|
|
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
|
|
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x float> @llvm.vp.floor.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 16 x float> %v
|
|
}
|
|
|
|
define <vscale x 1 x double> @vp_floor_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv1f64:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI34_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI34_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v9, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv1f64:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v9, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv1f64:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI34_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI34_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv1f64:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v9, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 1 x double> @llvm.vp.floor.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 %evl)
|
|
ret <vscale x 1 x double> %v
|
|
}
|
|
|
|
define <vscale x 1 x double> @vp_floor_nxv1f64_unmasked(<vscale x 1 x double> %va, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv1f64_unmasked:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI35_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI35_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v9, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv1f64_unmasked:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v9, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv1f64_unmasked:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI35_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI35_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv1f64_unmasked:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v9, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 1 x double> @llvm.vp.floor.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 1 x double> %v
|
|
}
|
|
|
|
define <vscale x 2 x double> @vp_floor_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv2f64:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI36_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI36_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v10, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv2f64:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v10, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv2f64:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI36_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI36_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv2f64:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v10, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 2 x double> @llvm.vp.floor.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)
|
|
ret <vscale x 2 x double> %v
|
|
}
|
|
|
|
define <vscale x 2 x double> @vp_floor_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv2f64_unmasked:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI37_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI37_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v10, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv2f64_unmasked:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v10, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv2f64_unmasked:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI37_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI37_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv2f64_unmasked:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v10, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 2 x double> @llvm.vp.floor.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 2 x double> %v
|
|
}
|
|
|
|
define <vscale x 4 x double> @vp_floor_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv4f64:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI38_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI38_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v12, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv4f64:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v12, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv4f64:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI38_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI38_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv4f64:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v12, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 4 x double> @llvm.vp.floor.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)
|
|
ret <vscale x 4 x double> %v
|
|
}
|
|
|
|
define <vscale x 4 x double> @vp_floor_nxv4f64_unmasked(<vscale x 4 x double> %va, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv4f64_unmasked:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI39_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI39_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v12, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv4f64_unmasked:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v12, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv4f64_unmasked:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI39_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI39_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv4f64_unmasked:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v12, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 4 x double> @llvm.vp.floor.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 4 x double> %v
|
|
}
|
|
|
|
define <vscale x 7 x double> @vp_floor_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv7f64:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI40_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI40_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v16, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv7f64:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v16, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv7f64:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI40_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI40_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv7f64:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v16, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 7 x double> @llvm.vp.floor.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)
|
|
ret <vscale x 7 x double> %v
|
|
}
|
|
|
|
define <vscale x 7 x double> @vp_floor_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv7f64_unmasked:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI41_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI41_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v16, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv7f64_unmasked:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v16, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv7f64_unmasked:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI41_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI41_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv7f64_unmasked:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v16, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 7 x double> @llvm.vp.floor.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 7 x double> %v
|
|
}
|
|
|
|
define <vscale x 8 x double> @vp_floor_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv8f64:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI42_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI42_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v16, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv8f64:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v16, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv8f64:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI42_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI42_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv8f64:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v16, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 8 x double> @llvm.vp.floor.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)
|
|
ret <vscale x 8 x double> %v
|
|
}
|
|
|
|
define <vscale x 8 x double> @vp_floor_nxv8f64_unmasked(<vscale x 8 x double> %va, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv8f64_unmasked:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI43_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI43_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v16, v8
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv8f64_unmasked:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v16, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv8f64_unmasked:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI43_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI43_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv8f64_unmasked:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v16, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 8 x double> @llvm.vp.floor.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 8 x double> %v
|
|
}
|
|
|
|
; Test splitting.
|
|
|
|
define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv16f64:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI44_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI44_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v24, v8
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
|
|
; RV32ZVFH-NEXT: vfabs.v v24, v16
|
|
; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
|
|
; RV32ZVFH-NEXT: vmv1r.v v0, v7
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv16f64:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v24, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
|
|
; RV64ZVFH-NEXT: vfabs.v v24, v16
|
|
; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
|
|
; RV64ZVFH-NEXT: vmv1r.v v0, v7
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv16f64:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI44_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI44_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv16f64:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 16 x double> @llvm.vp.floor.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)
|
|
ret <vscale x 16 x double> %v
|
|
}
|
|
|
|
define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {
|
|
; RV32ZVFH-LABEL: vp_floor_nxv16f64_unmasked:
|
|
; RV32ZVFH: # %bb.0:
|
|
; RV32ZVFH-NEXT: lui a0, %hi(.LCPI45_0)
|
|
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI45_0)(a0)
|
|
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFH-NEXT: vfabs.v v24, v8
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
|
|
; RV32ZVFH-NEXT: vfabs.v v24, v16
|
|
; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV32ZVFH-NEXT: fsrmi a0, 2
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
|
|
; RV32ZVFH-NEXT: vmv1r.v v0, v7
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; RV32ZVFH-NEXT: fsrm a0
|
|
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; RV32ZVFH-NEXT: ret
|
|
;
|
|
; RV64ZVFH-LABEL: vp_floor_nxv16f64_unmasked:
|
|
; RV64ZVFH: # %bb.0:
|
|
; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFH-NEXT: vfabs.v v24, v8
|
|
; RV64ZVFH-NEXT: li a0, 1075
|
|
; RV64ZVFH-NEXT: slli a0, a0, 52
|
|
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
|
|
; RV64ZVFH-NEXT: vfabs.v v24, v16
|
|
; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV64ZVFH-NEXT: fsrmi a0, 2
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
|
|
; RV64ZVFH-NEXT: vmv1r.v v0, v7
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; RV64ZVFH-NEXT: fsrm a0
|
|
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; RV64ZVFH-NEXT: ret
|
|
;
|
|
; RV32ZVFHMIN-LABEL: vp_floor_nxv16f64_unmasked:
|
|
; RV32ZVFHMIN: # %bb.0:
|
|
; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI45_0)
|
|
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI45_0)(a0)
|
|
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
|
|
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
|
|
; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
|
|
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; RV32ZVFHMIN-NEXT: fsrm a0
|
|
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; RV32ZVFHMIN-NEXT: ret
|
|
;
|
|
; RV64ZVFHMIN-LABEL: vp_floor_nxv16f64_unmasked:
|
|
; RV64ZVFHMIN: # %bb.0:
|
|
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
|
|
; RV64ZVFHMIN-NEXT: li a0, 1075
|
|
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
|
|
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
|
|
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
|
|
; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
|
|
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
|
|
; RV64ZVFHMIN-NEXT: fsrm a0
|
|
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
|
|
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
|
|
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
|
|
; RV64ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 16 x double> @llvm.vp.floor.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
|
|
ret <vscale x 16 x double> %v
|
|
}
|