derek.holloway
7502bf64a4
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49 lines
1.6 KiB
LLVM
49 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
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; Check that we are able to legalize scalable-vector loads that require widening.
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define <vscale x 3 x i8> @load_nxv3i8(ptr %ptr) {
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; CHECK-LABEL: load_nxv3i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: srli a2, a1, 3
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; CHECK-NEXT: srli a1, a1, 2
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; CHECK-NEXT: add a1, a1, a2
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <vscale x 3 x i8>, ptr %ptr
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ret <vscale x 3 x i8> %v
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}
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define <vscale x 5 x half> @load_nxv5f16(ptr %ptr) {
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; CHECK-LABEL: load_nxv5f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: srli a2, a1, 3
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; CHECK-NEXT: srli a1, a1, 1
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; CHECK-NEXT: add a1, a1, a2
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; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <vscale x 5 x half>, ptr %ptr
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ret <vscale x 5 x half> %v
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}
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define <vscale x 7 x half> @load_nxv7f16(ptr %ptr, ptr %out) {
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; CHECK-LABEL: load_nxv7f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: srli a3, a2, 3
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; CHECK-NEXT: sub a2, a2, a3
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; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vse16.v v8, (a1)
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; CHECK-NEXT: ret
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%v = load <vscale x 7 x half>, ptr %ptr
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store <vscale x 7 x half> %v, ptr %out
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ret <vscale x 7 x half> %v
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}
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