derek.holloway
7502bf64a4
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33 lines
1.1 KiB
LLVM
33 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
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; Check that we are able to legalize scalable-vector stores that require widening.
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define void @store_nxv3i8(<vscale x 3 x i8> %val, ptr %ptr) {
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; CHECK-LABEL: store_nxv3i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: srli a2, a1, 3
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; CHECK-NEXT: srli a1, a1, 2
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; CHECK-NEXT: add a1, a1, a2
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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store <vscale x 3 x i8> %val, ptr %ptr
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ret void
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}
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define void @store_nxv7f64(<vscale x 7 x double> %val, ptr %ptr) {
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; CHECK-LABEL: store_nxv7f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: srli a2, a1, 3
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; CHECK-NEXT: sub a1, a1, a2
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; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
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; CHECK-NEXT: vse64.v v8, (a0)
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; CHECK-NEXT: ret
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store <vscale x 7 x double> %val, ptr %ptr
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ret void
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}
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