derek.holloway
7502bf64a4
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364 lines
14 KiB
LLVM
364 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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define <1 x i1> @and_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_v1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <1 x i1> @llvm.vp.and.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)
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ret <1 x i1> %v
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}
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define <2 x i1> @and_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <2 x i1> @llvm.vp.and.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)
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ret <2 x i1> %v
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}
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define <4 x i1> @and_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_v4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <4 x i1> @llvm.vp.and.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)
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ret <4 x i1> %v
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}
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define <8 x i1> @and_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_v8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <8 x i1> @llvm.vp.and.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)
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ret <8 x i1> %v
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}
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define <16 x i1> @and_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_v16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <16 x i1> @llvm.vp.and.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)
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ret <16 x i1> %v
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}
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define <vscale x 1 x i1> @and_nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i1> @llvm.vp.and.nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 %evl)
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ret <vscale x 1 x i1> %v
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}
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define <vscale x 2 x i1> @and_nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i1> @llvm.vp.and.nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 %evl)
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ret <vscale x 2 x i1> %v
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}
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define <vscale x 4 x i1> @and_nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i1> @llvm.vp.and.nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 %evl)
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ret <vscale x 4 x i1> %v
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}
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define <vscale x 8 x i1> @and_nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i1> @llvm.vp.and.nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 %evl)
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ret <vscale x 8 x i1> %v
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}
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define <vscale x 16 x i1> @and_nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_nxv16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i1> @llvm.vp.and.nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 %evl)
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ret <vscale x 16 x i1> %v
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}
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define <vscale x 32 x i1> @and_nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_nxv32i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x i1> @llvm.vp.and.nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 %evl)
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ret <vscale x 32 x i1> %v
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}
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define <vscale x 64 x i1> @and_nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: and_nxv64i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmand.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 64 x i1> @llvm.vp.and.nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 %evl)
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ret <vscale x 64 x i1> %v
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}
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define <1 x i1> @or_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_v1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <1 x i1> @llvm.vp.or.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)
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ret <1 x i1> %v
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}
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define <2 x i1> @or_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <2 x i1> @llvm.vp.or.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)
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ret <2 x i1> %v
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}
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define <4 x i1> @or_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_v4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <4 x i1> @llvm.vp.or.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)
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ret <4 x i1> %v
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}
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define <8 x i1> @or_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_v8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <8 x i1> @llvm.vp.or.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)
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ret <8 x i1> %v
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}
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define <16 x i1> @or_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_v16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <16 x i1> @llvm.vp.or.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)
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ret <16 x i1> %v
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}
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define <vscale x 1 x i1> @or_nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i1> @llvm.vp.or.nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 %evl)
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ret <vscale x 1 x i1> %v
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}
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define <vscale x 2 x i1> @or_nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i1> @llvm.vp.or.nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 %evl)
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ret <vscale x 2 x i1> %v
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}
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define <vscale x 4 x i1> @or_nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i1> @llvm.vp.or.nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 %evl)
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ret <vscale x 4 x i1> %v
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}
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define <vscale x 8 x i1> @or_nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i1> @llvm.vp.or.nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 %evl)
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ret <vscale x 8 x i1> %v
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}
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define <vscale x 16 x i1> @or_nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_nxv16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i1> @llvm.vp.or.nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 %evl)
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ret <vscale x 16 x i1> %v
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}
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define <vscale x 32 x i1> @or_nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_nxv32i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x i1> @llvm.vp.or.nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 %evl)
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ret <vscale x 32 x i1> %v
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}
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define <vscale x 64 x i1> @or_nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: or_nxv64i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 64 x i1> @llvm.vp.or.nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 %evl)
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ret <vscale x 64 x i1> %v
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}
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define <1 x i1> @xor_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: xor_v1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <1 x i1> @llvm.vp.xor.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)
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ret <1 x i1> %v
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}
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define <2 x i1> @xor_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: xor_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <2 x i1> @llvm.vp.xor.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)
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ret <2 x i1> %v
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}
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define <4 x i1> @xor_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: xor_v4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <4 x i1> @llvm.vp.xor.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)
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ret <4 x i1> %v
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}
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define <8 x i1> @xor_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: xor_v8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <8 x i1> @llvm.vp.xor.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)
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ret <8 x i1> %v
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}
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define <16 x i1> @xor_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {
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; CHECK-LABEL: xor_v16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <16 x i1> @llvm.vp.xor.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)
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ret <16 x i1> %v
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}
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define <vscale x 1 x i1> @xor_nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 zeroext %evl) {
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|
; CHECK-LABEL: xor_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i1> @llvm.vp.xor.nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 %evl)
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ret <vscale x 1 x i1> %v
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}
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|
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define <vscale x 2 x i1> @xor_nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 zeroext %evl) {
|
|
; CHECK-LABEL: xor_nxv2i1:
|
|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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|
; CHECK-NEXT: vmxor.mm v0, v0, v8
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|
; CHECK-NEXT: ret
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|
%v = call <vscale x 2 x i1> @llvm.vp.xor.nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 %evl)
|
|
ret <vscale x 2 x i1> %v
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|
}
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|
|
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define <vscale x 4 x i1> @xor_nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 zeroext %evl) {
|
|
; CHECK-LABEL: xor_nxv4i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v0, v0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 4 x i1> @llvm.vp.xor.nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 %evl)
|
|
ret <vscale x 4 x i1> %v
|
|
}
|
|
|
|
define <vscale x 8 x i1> @xor_nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 zeroext %evl) {
|
|
; CHECK-LABEL: xor_nxv8i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v0, v0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 8 x i1> @llvm.vp.xor.nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 %evl)
|
|
ret <vscale x 8 x i1> %v
|
|
}
|
|
|
|
define <vscale x 16 x i1> @xor_nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 zeroext %evl) {
|
|
; CHECK-LABEL: xor_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v0, v0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x i1> @llvm.vp.xor.nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 %evl)
|
|
ret <vscale x 16 x i1> %v
|
|
}
|
|
|
|
define <vscale x 32 x i1> @xor_nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 zeroext %evl) {
|
|
; CHECK-LABEL: xor_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v0, v0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 32 x i1> @llvm.vp.xor.nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 %evl)
|
|
ret <vscale x 32 x i1> %v
|
|
}
|
|
|
|
define <vscale x 64 x i1> @xor_nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 zeroext %evl) {
|
|
; CHECK-LABEL: xor_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v0, v0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 64 x i1> @llvm.vp.xor.nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 %evl)
|
|
ret <vscale x 64 x i1> %v
|
|
}
|