derek.holloway
7502bf64a4
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112 lines
4.2 KiB
LLVM
112 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \
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; RUN: < %s | FileCheck %s
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define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tumu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
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; CHECK-LABEL: intrinsic_vslide1down_mask_tumu_vx_nxv1i64_nxv1i64_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma
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; CHECK-NEXT: slli a3, a3, 1
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; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma
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; CHECK-NEXT: vslide1down.vx v9, v9, a0
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; CHECK-NEXT: vslide1down.vx v9, v9, a1
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
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<vscale x 1 x i64> %0,
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<vscale x 1 x i64> %1,
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i64 %2,
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<vscale x 1 x i1> %3,
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i32 %4, i32 0)
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ret <vscale x 1 x i64> %a
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}
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define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tamu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
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; CHECK-LABEL: intrinsic_vslide1down_mask_tamu_vx_nxv1i64_nxv1i64_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma
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; CHECK-NEXT: slli a3, a3, 1
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; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma
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; CHECK-NEXT: vslide1down.vx v9, v9, a0
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; CHECK-NEXT: vslide1down.vx v9, v9, a1
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
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<vscale x 1 x i64> %0,
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<vscale x 1 x i64> %1,
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i64 %2,
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<vscale x 1 x i1> %3,
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i32 %4, i32 1)
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ret <vscale x 1 x i64> %a
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}
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; Fallback vslide1 to mask undisturbed until InsertVSETVLI supports mask agnostic.
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define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
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; CHECK-LABEL: intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma
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; CHECK-NEXT: slli a3, a3, 1
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; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma
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; CHECK-NEXT: vslide1down.vx v9, v9, a0
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; CHECK-NEXT: vslide1down.vx v9, v9, a1
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
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<vscale x 1 x i64> %0,
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<vscale x 1 x i64> %1,
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i64 %2,
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<vscale x 1 x i1> %3,
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i32 %4, i32 2)
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ret <vscale x 1 x i64> %a
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}
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; Fallback vslide1 to mask undisturbed until InsertVSETVLI supports mask agnostic.
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define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
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; CHECK-LABEL: intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma
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; CHECK-NEXT: slli a2, a2, 1
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; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
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; CHECK-NEXT: vslide1down.vx v8, v8, a0
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; CHECK-NEXT: vslide1down.vx v8, v8, a1
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
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<vscale x 1 x i64> poison,
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<vscale x 1 x i64> %0,
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i64 %1,
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<vscale x 1 x i1> %2,
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i32 %3, i32 3)
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ret <vscale x 1 x i64> %a
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}
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define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tama_undef_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vslide1down_mask_tama_undef_mask_vx_nxv1i64_nxv1i64_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma
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; CHECK-NEXT: slli a2, a2, 1
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; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
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; CHECK-NEXT: vslide1down.vx v8, v8, a0
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; CHECK-NEXT: vslide1down.vx v8, v8, a1
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
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<vscale x 1 x i64> poison,
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<vscale x 1 x i64> %0,
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i64 %1,
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<vscale x 1 x i1> poison,
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i32 %2, i32 3)
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ret <vscale x 1 x i64> %a
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}
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