derek.holloway
7502bf64a4
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192 lines
6.7 KiB
LLVM
192 lines
6.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvfbfa \
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; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvfbfa \
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; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
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define <vscale x 1 x bfloat> @test_half_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {
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; CHECK-LABEL: test_half_bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fsrmi a2, 0
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v10, v10, v11
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; CHECK-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: fsrm a2
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; CHECK-NEXT: vse16.v v10, (a1)
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
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<vscale x 1 x half> poison,
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<vscale x 1 x half> %3,
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<vscale x 1 x half> %4,
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iXLen 0, iXLen %2)
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%b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
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<vscale x 1 x bfloat> poison,
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<vscale x 1 x bfloat> %0,
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<vscale x 1 x bfloat> %1,
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iXLen 0, iXLen %2)
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call void @llvm.riscv.vse(<vscale x 1 x half> %a, ptr %ptr, iXLen %2)
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ret <vscale x 1 x bfloat> %b
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}
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define <vscale x 1 x bfloat> @test_i32_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i32> %3, <vscale x 1 x i32> %4, ptr %ptr) nounwind {
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; CHECK-LABEL: test_i32_bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vadd.vv v10, v10, v11
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; CHECK-NEXT: fsrmi a0, 0
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; CHECK-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: vse32.v v10, (a1)
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
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<vscale x 1 x i32> poison,
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<vscale x 1 x i32> %3,
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<vscale x 1 x i32> %4,
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iXLen %2)
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%b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
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<vscale x 1 x bfloat> poison,
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<vscale x 1 x bfloat> %0,
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<vscale x 1 x bfloat> %1,
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iXLen 0, iXLen %2)
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call void @llvm.riscv.vse(<vscale x 1 x i32> %a, ptr %ptr, iXLen %2)
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ret <vscale x 1 x bfloat> %b
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}
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define <vscale x 1 x bfloat> @test_half_bf16_half(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {
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; CHECK-LABEL: test_half_bf16_half:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fsrmi a2, 0
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v10, v10, v11
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; CHECK-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v9, v10, v11
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; CHECK-NEXT: fsrm a2
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vse16.v v9, (a1)
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
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<vscale x 1 x half> poison,
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<vscale x 1 x half> %3,
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<vscale x 1 x half> %4,
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iXLen 0, iXLen %2)
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%b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
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<vscale x 1 x bfloat> poison,
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<vscale x 1 x bfloat> %0,
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<vscale x 1 x bfloat> %1,
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iXLen 0, iXLen %2)
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%c = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
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<vscale x 1 x half> poison,
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<vscale x 1 x half> %a,
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<vscale x 1 x half> %4,
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iXLen 0, iXLen %2)
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store <vscale x 1 x half> %c, ptr %ptr
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ret <vscale x 1 x bfloat> %b
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}
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define <vscale x 1 x bfloat> @test_bf16_half_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {
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; CHECK-LABEL: test_bf16_half_bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fsrmi a2, 0
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; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v10, v10, v11
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; CHECK-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: fsrm a2
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; CHECK-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
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; CHECK-NEXT: vse16.v v10, (a1)
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
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<vscale x 1 x bfloat> poison,
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<vscale x 1 x bfloat> %0,
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<vscale x 1 x bfloat> %1,
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iXLen 0, iXLen %2)
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%b = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
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<vscale x 1 x half> poison,
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<vscale x 1 x half> %3,
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<vscale x 1 x half> %4,
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iXLen 0, iXLen %2)
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%c = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
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<vscale x 1 x bfloat> poison,
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<vscale x 1 x bfloat> %a,
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<vscale x 1 x bfloat> %1,
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iXLen 0, iXLen %2)
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store <vscale x 1 x half> %b, ptr %ptr
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ret <vscale x 1 x bfloat> %c
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}
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define <vscale x 1 x bfloat> @test_bf16_i16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i16> %3, <vscale x 1 x i16> %4, ptr %ptr) nounwind {
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; CHECK-LABEL: test_bf16_i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fsrmi a2, 0
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; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: vadd.vv v9, v10, v11
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; CHECK-NEXT: fsrm a2
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; CHECK-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
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; CHECK-NEXT: vse16.v v9, (a1)
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
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<vscale x 1 x bfloat> poison,
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<vscale x 1 x bfloat> %0,
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<vscale x 1 x bfloat> %1,
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iXLen 0, iXLen %2)
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%b = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
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<vscale x 1 x i16> poison,
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<vscale x 1 x i16> %3,
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<vscale x 1 x i16> %4,
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iXLen %2)
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store <vscale x 1 x i16> %b, ptr %ptr
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ret <vscale x 1 x bfloat> %a
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}
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define <8 x i64> @test_bf16_i64(<8 x i64> %v, <8 x bfloat> %v2, ptr %p) {
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; CHECK-LABEL: test_bf16_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
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; CHECK-NEXT: vid.v v16
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; CHECK-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
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; CHECK-NEXT: vfmv.f.s fa5, v12
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; CHECK-NEXT: fmv.w.x fa4, zero
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vadd.vv v12, v16, v16
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
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; CHECK-NEXT: vadd.vv v8, v8, v12
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; CHECK-NEXT: fadd.s fa5, fa5, fa4
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; CHECK-NEXT: fcvt.bf16.s fa5, fa5
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; CHECK-NEXT: fsh fa5, 0(a0)
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; CHECK-NEXT: ret
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%vp2 = add <8 x i64> %v, <i64 poison, i64 2, i64 4, i64 6, i64 8, i64 10, i64 12, i64 14>
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%sum2 = fadd <8 x bfloat> zeroinitializer, %v2
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%s0 = extractelement <8 x bfloat> %sum2, i64 0
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store bfloat %s0, ptr %p
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ret <8 x i64> %vp2
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}
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