derek.holloway
7502bf64a4
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38 lines
2.1 KiB
LLVM
38 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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@__const.test.var_45 = private unnamed_addr constant [2 x i8] c"\D1S", align 1
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@__const.test.var_101 = private unnamed_addr constant [2 x i8] c"\830", align 1
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define dso_local void @test(ptr nocapture noundef %var_99) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, %hi(.L__const.test.var_45)
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; CHECK-NEXT: addi a1, a1, %lo(.L__const.test.var_45)
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; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a1)
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; CHECK-NEXT: lui a1, %hi(.L__const.test.var_101)
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; CHECK-NEXT: addi a1, a1, %lo(.L__const.test.var_101)
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; CHECK-NEXT: vle8.v v12, (a1)
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; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: csrwi vxrm, 0
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; CHECK-NEXT: vmul.vx v16, v8, a1
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; CHECK-NEXT: vmv.x.s a1, v16
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; CHECK-NEXT: vmsleu.vx v0, v8, a1
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; CHECK-NEXT: vssra.vv v8, v12, v8
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; CHECK-NEXT: vmerge.vvm v8, v8, v8, v0
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8> poison, ptr nonnull @__const.test.var_45, i64 2)
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%1 = tail call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 1, i64 2)
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%2 = tail call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8> poison, ptr nonnull @__const.test.var_101, i64 2)
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%3 = tail call i64 @llvm.riscv.vsetvli.i64(i64 32, i64 0, i64 2)
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%4 = tail call i8 @llvm.riscv.vmv.x.s.nxv32i8(<vscale x 32 x i8> %1)
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%5 = tail call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %2, <vscale x 32 x i8> %0, i64 0, i64 2)
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%6 = tail call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8.i64(<vscale x 32 x i8> %0, i8 %4, i64 2)
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%7 = tail call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %5, <vscale x 32 x i8> %5, <vscale x 32 x i1> %6, i64 2)
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tail call void @llvm.riscv.vse.nxv32i8.i64(<vscale x 32 x i8> %7, ptr %var_99, i64 2)
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ret void
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}
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