derek.holloway
7502bf64a4
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294 lines
10 KiB
LLVM
294 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 4 x i32> @test_vloxei(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
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; CHECK-LABEL: test_vloxei:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v8
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vloxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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%res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @test_vloxei2(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
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; CHECK-LABEL: test_vloxei2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v8
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; CHECK-NEXT: vsll.vi v12, v12, 14
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vloxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 14)
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%res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @test_vloxei3(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
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; CHECK-LABEL: test_vloxei3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v8
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; CHECK-NEXT: vsll.vi v12, v12, 26
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vloxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 26)
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%res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl)
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ret <vscale x 4 x i32> %res
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}
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; Test use vp.zext to extend.
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define <vscale x 4 x i32> @test_vloxei4(ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: test_vloxei4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v8
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vloxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = call <vscale x 4 x i64> @llvm.vp.zext.nxvi64.nxv1i8(<vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i32 %vl)
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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%vl.i64 = zext i32 %vl to i64
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%res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl.i64)
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ret <vscale x 4 x i32> %res
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}
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; Test orignal extnened type is enough narrow.
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define <vscale x 4 x i32> @test_vloxei5(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
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; CHECK-LABEL: test_vloxei5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
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; CHECK-NEXT: vzext.vf2 v9, v8
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; CHECK-NEXT: vsll.vi v10, v9, 12
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vloxei16.v v8, (a0), v10
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i16>
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%shl = shl <vscale x 4 x i16> %offset.ext, splat (i16 12)
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%res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i16> %shl,
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i64 %vl)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @test_vloxei6(ptr %ptr, <vscale x 4 x i7> %offset, i64 %vl) {
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; CHECK-LABEL: test_vloxei6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a2, 127
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
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; CHECK-NEXT: vand.vx v12, v8, a2
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v8, v12
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; CHECK-NEXT: vsll.vi v12, v8, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vloxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i7> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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%res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @test_vloxei7(ptr %ptr, <vscale x 4 x i1> %offset, i64 %vl) {
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; CHECK-LABEL: test_vloxei7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
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; CHECK-NEXT: vsll.vi v12, v8, 2
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vloxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i1> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 2)
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%res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @test_vloxei_mask(ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {
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; CHECK-LABEL: test_vloxei_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v8
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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%res = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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<vscale x 4 x i1> %m,
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i64 %vl, i64 1)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @test_vluxei(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
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; CHECK-LABEL: test_vluxei:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v8
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vluxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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%res = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @test_vluxei_mask(ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {
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; CHECK-LABEL: test_vluxei_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v8
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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%res = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64(
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<vscale x 4 x i32> poison,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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<vscale x 4 x i1> %m,
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i64 %vl, i64 1)
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ret <vscale x 4 x i32> %res
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}
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define void @test_vsoxei(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
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; CHECK-LABEL: test_vsoxei:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v10
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vsoxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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call void @llvm.riscv.vsoxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> %val,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl)
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ret void
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}
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define void @test_vsoxei_mask(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {
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; CHECK-LABEL: test_vsoxei_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v10
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i64(
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<vscale x 4 x i32> %val,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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<vscale x 4 x i1> %m,
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i64 %vl)
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ret void
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}
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define void @test_vsuxei(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
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; CHECK-LABEL: test_vsuxei:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v10
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vsuxei64.v v8, (a0), v12
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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call void @llvm.riscv.vsuxei.nxv4i32.nxv4i64(
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<vscale x 4 x i32> %val,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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i64 %vl)
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ret void
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}
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define void @test_vsuxei_mask(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {
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; CHECK-LABEL: test_vsuxei_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
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; CHECK-NEXT: vzext.vf8 v12, v10
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; CHECK-NEXT: vsll.vi v12, v12, 4
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t
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; CHECK-NEXT: ret
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entry:
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%offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>
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%shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)
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call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i64(
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<vscale x 4 x i32> %val,
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ptr %ptr,
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<vscale x 4 x i64> %shl,
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<vscale x 4 x i1> %m,
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i64 %vl)
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ret void
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}
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