derek.holloway
7502bf64a4
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80 lines
3.4 KiB
LLVM
80 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=riscv32 -mattr=+v -o - %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -o - %s | FileCheck %s
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define <4 x i32> @partial_reduce_add_v4i32_v4i32(<4 x i32> %accumulator, <4 x i32> %0) {
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; CHECK-LABEL: partial_reduce_add_v4i32_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> %accumulator, <4 x i32> %0)
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ret <4 x i32> %partial.reduce
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}
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define <4 x i32> @partial_reduce_add_v4i32_v8i32(<4 x i32> %accumulator, <8 x i32> %0) {
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; CHECK-LABEL: partial_reduce_add_v4i32_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vadd.vv v12, v8, v10
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; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v10, 4
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v12
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> %accumulator, <8 x i32> %0)
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ret <4 x i32> %partial.reduce
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}
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define <vscale x 4 x i32> @partial_reduce_add_nvx4i32_nvx4i32(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0) {
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; CHECK-LABEL: partial_reduce_add_nvx4i32_nvx4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v10
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0)
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ret <vscale x 4 x i32> %partial.reduce
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}
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define <vscale x 4 x i32> @partial_reduce_add_nvx4i32_nvx8i32(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0) {
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; CHECK-LABEL: partial_reduce_add_nvx4i32_nvx8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v12
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; CHECK-NEXT: vadd.vv v8, v14, v8
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0)
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ret <vscale x 4 x i32> %partial.reduce
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}
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define <vscale x 4 x i32> @partial_reduce_add_nvx4i32_nvx16i32(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0) {
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; CHECK-LABEL: partial_reduce_add_nvx4i32_nvx16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v10, v18, v20
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; CHECK-NEXT: vadd.vv v8, v8, v16
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; CHECK-NEXT: vadd.vv v8, v22, v8
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0)
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ret <vscale x 4 x i32> %partial.reduce
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}
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define <vscale x 8 x i32> @partial_reduce_add_nvx8i32_nvx16i32(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0) {
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; CHECK-LABEL: partial_reduce_add_nvx8i32_nvx16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v16
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; CHECK-NEXT: vadd.vv v8, v20, v8
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <vscale x 8 x i32> @llvm.vector.partial.reduce.add(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0)
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ret <vscale x 8 x i32> %partial.reduce
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}
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