derek.holloway
7502bf64a4
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25 lines
1.3 KiB
LLVM
25 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mattr=+v < %s -verify-machineinstrs | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
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target triple = "riscv64-unknown-linux-gnu"
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define void @m(<vscale x 4 x i1> %0) {
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; CHECK-LABEL: m:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vlse32.v v8, (zero), zero, v0.t
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vse32.v v8, (zero)
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; CHECK-NEXT: ret
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entry:
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%broadcast.splatinsert184 = insertelement <vscale x 4 x ptr> zeroinitializer, ptr null, i64 0
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%broadcast.splat185 = shufflevector <vscale x 4 x ptr> %broadcast.splatinsert184, <vscale x 4 x ptr> zeroinitializer, <vscale x 4 x i32> zeroinitializer
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%wide.masked.gather186 = tail call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> %broadcast.splat185, i32 4, <vscale x 4 x i1> %0, <vscale x 4 x i32> zeroinitializer)
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%predphi187 = select <vscale x 4 x i1> %0, <vscale x 4 x i32> %wide.masked.gather186, <vscale x 4 x i32> zeroinitializer
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%1 = extractelement <vscale x 4 x i32> %predphi187, i32 0
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store i32 %1, ptr null, align 4
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ret void
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}
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