TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/pr61561.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s

define <vscale x 4 x i8> @foo(ptr %p) {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vl1re16.v v10, (a0)
; CHECK-NEXT:    lui a0, 4
; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT:    vmv.v.x v8, a0
; CHECK-NEXT:    li a0, 248
; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT:    vsll.vi v12, v10, 3
; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT:    vzext.vf2 v10, v12
; CHECK-NEXT:    vand.vx v10, v10, a0
; CHECK-NEXT:    lui a0, 1
; CHECK-NEXT:    addi a0, a0, -361
; CHECK-NEXT:    vmacc.vx v8, a0, v10
; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT:    vnsrl.wi v10, v8, 15
; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v10, 0
; CHECK-NEXT:    ret
  %i13 = load <vscale x 4 x i16>, ptr %p, align 2
  %i14 = zext <vscale x 4 x i16> %i13 to <vscale x 4 x i32>
  %i15 = shl nuw nsw <vscale x 4 x i32> %i14, splat (i32 3)
  %i16 = and <vscale x 4 x i32> %i15, splat (i32 248)
  %i17 = mul nuw nsw <vscale x 4 x i32> %i16, splat (i32 3735)
  %i18 = add nuw nsw <vscale x 4 x i32> %i17, splat (i32 16384)
  %i21 = lshr <vscale x 4 x i32> %i18, splat (i32 15)
  %i22 = trunc <vscale x 4 x i32> %i21 to <vscale x 4 x i8>
  ret <vscale x 4 x i8> %i22
}