derek.holloway
7502bf64a4
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70 lines
2.7 KiB
LLVM
70 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -target-abi=lp64d | FileCheck %s
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define <4 x float> @foo(ptr %0) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -48
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; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: lhu s0, 0(a0)
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; CHECK-NEXT: lhu s1, 2(a0)
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; CHECK-NEXT: lhu s2, 4(a0)
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; CHECK-NEXT: lhu a0, 6(a0)
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; CHECK-NEXT: fmv.w.x fa0, a0
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; CHECK-NEXT: call __extendhfsf2
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; CHECK-NEXT: fmv.w.x fa5, s2
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
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; CHECK-NEXT: fmv.s fa0, fa5
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; CHECK-NEXT: call __extendhfsf2
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
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; CHECK-NEXT: vslideup.vi v8, v9, 1
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
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; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
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; CHECK-NEXT: fmv.w.x fa0, s1
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; CHECK-NEXT: call __extendhfsf2
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; CHECK-NEXT: fmv.w.x fa5, s0
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
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; CHECK-NEXT: fmv.s fa0, fa5
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; CHECK-NEXT: call __extendhfsf2
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
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; CHECK-NEXT: vslideup.vi v8, v9, 1
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
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; CHECK-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 2
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 1
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 48
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; CHECK-NEXT: ret
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%2 = load <4 x half>, ptr %0, align 2
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%3 = fpext <4 x half> %2 to <4 x float>
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ret <4 x float> %3
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}
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