derek.holloway
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51 lines
2.0 KiB
LLVM
51 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck %s
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; This showcases a miscompile that was fixed in #83107:
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; - The memset will be type-legalized to a 512 bit store + 2 x 128 bit stores.
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; - the load and store of q aliases the upper 128 bits store of p.
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; - The aliasing 128 bit store will be between the chain of the scalar
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; load/store:
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;
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; t54: ch = store<(store (s512) into %ir.p, align 1)> t0, ...
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; t51: ch = store<(store (s128) into %ir.p + 64, align 1)> t0, ...
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;
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; t44: i64,ch = load<(load (s32) from %ir.q), sext from i32> t0, ...
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; t50: ch = store<(store (s128) into %ir.p + 80, align 1)> t44:1, ...
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; t46: ch = store<(store (s32) into %ir.q), trunc to i32> t50, ...
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;
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; Previously, the scalar load/store was incorrectly combined away:
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;
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; t54: ch = store<(store (s512) into %ir.p, align 1)> t0, ...
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; t51: ch = store<(store (s128) into %ir.p + 64, align 1)> t0, ...
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;
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; // MISSING
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; t50: ch = store<(store (s128) into %ir.p + 80, align 1)> t44:1, ...
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; // MISSING
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;
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; - We need to compile with an exact VLEN so that we select an ISD::STORE node
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; which triggers the combine
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; - The miscompile doesn't happen if we use separate GEPs as we need the stores
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; to share the same MachinePointerInfo
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define void @aliasing(ptr %p) {
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; CHECK-LABEL: aliasing:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 84(a0)
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; CHECK-NEXT: addi a2, a0, 80
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vs1r.v v8, (a2)
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; CHECK-NEXT: addi a2, a0, 64
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; CHECK-NEXT: vs1r.v v8, (a2)
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; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vs4r.v v8, (a0)
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; CHECK-NEXT: sw a1, 84(a0)
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; CHECK-NEXT: ret
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%q = getelementptr inbounds i8, ptr %p, i64 84
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%tmp = load i32, ptr %q
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tail call void @llvm.memset.p0.i64(ptr %p, i8 0, i64 96, i1 false)
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store i32 %tmp, ptr %q
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ret void
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}
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