derek.holloway
7502bf64a4
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65 lines
2.2 KiB
LLVM
65 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
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define i1 @foo(<vscale x 16 x i8> %x, i64 %y) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a2, a1, 4
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; CHECK-NEXT: addi a2, a2, -1
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; CHECK-NEXT: bltu a0, a2, .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: addi sp, sp, -80
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; CHECK-NEXT: .cfi_def_cfa_offset 80
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; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset ra, -8
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; CHECK-NEXT: .cfi_offset s0, -16
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; CHECK-NEXT: addi s0, sp, 80
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; CHECK-NEXT: .cfi_def_cfa s0, 0
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: slli a2, a2, 4
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; CHECK-NEXT: sub sp, sp, a2
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; CHECK-NEXT: andi sp, sp, -64
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; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: addi a2, sp, 64
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: vmv.v.i v16, 0
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; CHECK-NEXT: add a0, a2, a0
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; CHECK-NEXT: add a1, a2, a1
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; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
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; CHECK-NEXT: vs8r.v v24, (a1)
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; CHECK-NEXT: vs8r.v v8, (a2)
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; CHECK-NEXT: lbu a0, 0(a0)
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; CHECK-NEXT: addi sp, s0, -80
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; CHECK-NEXT: .cfi_def_cfa sp, 80
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; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
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; CHECK-NEXT: .cfi_restore ra
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; CHECK-NEXT: .cfi_restore s0
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; CHECK-NEXT: addi sp, sp, 80
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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%a = bitcast <vscale x 16 x i8> %x to <vscale x 128 x i1>
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%b = extractelement <vscale x 128 x i1> %a, i64 %y
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ret i1 %b
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}
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define i8 @bar(<vscale x 128 x i1> %x, i64 %y) {
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; CHECK-LABEL: bar:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma
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; CHECK-NEXT: vmv1r.v v1, v8
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; CHECK-NEXT: vslidedown.vx v8, v0, a0
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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%a = bitcast <vscale x 128 x i1> %x to <vscale x 16 x i8>
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%b = extractelement <vscale x 16 x i8> %a, i64 %y
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ret i8 %b
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}
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