derek.holloway
7502bf64a4
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401 lines
15 KiB
LLVM
401 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
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define void @vid(ptr %p) {
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; CHECK-LABEL: vid:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v8, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: ret
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%vid = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(<vscale x 8 x i64> poison, i64 -1)
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store volatile <vscale x 8 x i64> %vid, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vid, ptr %p
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ret void
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}
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define void @vid_passthru(ptr %p, <vscale x 8 x i64> %v) {
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; CHECK-LABEL: vid_passthru:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; CHECK-NEXT: vsetivli zero, 1, e64, m8, tu, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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%vid = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(<vscale x 8 x i64> %v, i64 1)
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store volatile <vscale x 8 x i64> %vid, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vid, ptr %p
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ret void
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}
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define void @vmv.v.i(ptr %p) {
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; CHECK-LABEL: vmv.v.i:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 1
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v8, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vmv.v.i v8, 1
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: ret
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%vmv.v.i = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(<vscale x 8 x i64> poison, i64 1, i64 -1)
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store volatile <vscale x 8 x i64> %vmv.v.i, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vmv.v.i, ptr %p
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ret void
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}
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define void @vmv.v.x_needs_extended(ptr %p, i64 %x) {
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; CHECK-LABEL: vmv.v.x_needs_extended:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: slli a2, a2, 3
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; CHECK-NEXT: sub sp, sp, a2
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a1
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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%vmv.v.x = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(<vscale x 8 x i64> poison, i64 %x, i64 -1)
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store volatile <vscale x 8 x i64> %vmv.v.x, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vmv.v.x, ptr %p
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ret void
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}
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define void @vmv.v.x_live(ptr %p, i64 %x) {
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; CHECK-LABEL: vmv.v.x_live:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a1
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v8, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vmv.v.x v8, a1
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%vmv.v.x = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(<vscale x 8 x i64> poison, i64 %x, i64 -1)
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store volatile <vscale x 8 x i64> %vmv.v.x, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vmv.v.x, ptr %p
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store volatile i64 %x, ptr %p
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ret void
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}
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define void @vfmv.v.f(ptr %p, double %x) {
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; CHECK-LABEL: vfmv.v.f:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; CHECK-NEXT: vfmv.v.f v8, fa0
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v8, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vfmv.v.f v8, fa0
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: fsd fa0, 0(a0)
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; CHECK-NEXT: ret
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%vfmv.v.f = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64(<vscale x 8 x double> poison, double %x, i64 -1)
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store volatile <vscale x 8 x double> %vfmv.v.f, ptr %p
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%a = load volatile <vscale x 8 x double>, ptr %p
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%b = load volatile <vscale x 8 x double>, ptr %p
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%c = load volatile <vscale x 8 x double>, ptr %p
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%d = load volatile <vscale x 8 x double>, ptr %p
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store volatile <vscale x 8 x double> %d, ptr %p
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store volatile <vscale x 8 x double> %c, ptr %p
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store volatile <vscale x 8 x double> %b, ptr %p
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store volatile <vscale x 8 x double> %a, ptr %p
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store volatile <vscale x 8 x double> %vfmv.v.f, ptr %p
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store volatile double %x, ptr %p
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ret void
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}
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define void @vmv.s.x(ptr %p, i64 %x) {
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; CHECK-LABEL: vmv.s.x:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v8, a1
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v8, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vmv.s.x v8, a1
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%vmv.s.x = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> poison, i64 %x, i64 -1)
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store volatile <vscale x 8 x i64> %vmv.s.x, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vmv.s.x, ptr %p
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store volatile i64 %x, ptr %p
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ret void
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}
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define void @vfmv.s.f(ptr %p, double %x) {
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; CHECK-LABEL: vfmv.s.f:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v8, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: fsd fa0, 0(a0)
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; CHECK-NEXT: ret
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%vfmv.s.f = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> poison, double %x, i64 -1)
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store volatile <vscale x 8 x double> %vfmv.s.f, ptr %p
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%a = load volatile <vscale x 8 x double>, ptr %p
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%b = load volatile <vscale x 8 x double>, ptr %p
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%c = load volatile <vscale x 8 x double>, ptr %p
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%d = load volatile <vscale x 8 x double>, ptr %p
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store volatile <vscale x 8 x double> %d, ptr %p
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store volatile <vscale x 8 x double> %c, ptr %p
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store volatile <vscale x 8 x double> %b, ptr %p
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store volatile <vscale x 8 x double> %a, ptr %p
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store volatile <vscale x 8 x double> %vfmv.s.f, ptr %p
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store volatile double %x, ptr %p
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ret void
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}
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; This test is fairly fragile, but it's trying to cover the case which
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; caused the revert of bba9172 due to interaction with how rematerialize
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; instructions are pruned from the original live interval. In the result
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; below, we remat the vmv.v.x into the loop, but fail to remat the vmv.v.x
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; a second time after further splitting it's live range. We shouldn't need
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; to spill it to the stack at all.
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define i64 @dual_remat(i64 %0, <vscale x 16 x i64> %1, <vscale x 16 x i64> %2, ptr %p) #0 {
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; CHECK-LABEL: dual_remat:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a2, a1, 4
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; CHECK-NEXT: add a1, a2, a1
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: add a1, sp, a1
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; CHECK-NEXT: addi a1, a1, 16
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; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
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; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v24, 0
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: srli a1, a2, 3
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; CHECK-NEXT: slli a2, a2, 3
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|
; CHECK-NEXT: add a2, a3, a2
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|
; CHECK-NEXT: vmv.v.i v0, 0
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; CHECK-NEXT: .LBB8_1: # %vector.body
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|
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vmv.v.x v8, a0
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|
; CHECK-NEXT: vand.vv v16, v0, v8
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|
; CHECK-NEXT: vmv8r.v v8, v24
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|
; CHECK-NEXT: vmsne.vi v24, v16, 0
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|
; CHECK-NEXT: csrr a4, vlenb
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|
; CHECK-NEXT: slli a4, a4, 4
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|
; CHECK-NEXT: add a4, sp, a4
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|
; CHECK-NEXT: addi a4, a4, 16
|
|
; CHECK-NEXT: vs1r.v v24, (a4) # vscale x 8-byte Folded Spill
|
|
; CHECK-NEXT: vmv8r.v v24, v8
|
|
; CHECK-NEXT: vmv.v.x v8, a0
|
|
; CHECK-NEXT: vand.vv v16, v24, v8
|
|
; CHECK-NEXT: vmsne.vi v8, v16, 0
|
|
; CHECK-NEXT: csrr a4, vlenb
|
|
; CHECK-NEXT: slli a4, a4, 4
|
|
; CHECK-NEXT: add a4, sp, a4
|
|
; CHECK-NEXT: addi a4, a4, 16
|
|
; CHECK-NEXT: vl1r.v v9, (a4) # vscale x 8-byte Folded Reload
|
|
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v9, v8, a1
|
|
; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vcpop.m a4, v9
|
|
; CHECK-NEXT: vsetvli a5, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v8, a0
|
|
; CHECK-NEXT: vs8r.v v8, (a3)
|
|
; CHECK-NEXT: vs8r.v v8, (a2)
|
|
; CHECK-NEXT: addi a5, sp, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vor.vv v0, v0, v8
|
|
; CHECK-NEXT: csrr a5, vlenb
|
|
; CHECK-NEXT: slli a5, a5, 3
|
|
; CHECK-NEXT: add a5, sp, a5
|
|
; CHECK-NEXT: addi a5, a5, 16
|
|
; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
|
|
; CHECK-NEXT: vor.vv v24, v24, v8
|
|
; CHECK-NEXT: beqz a4, .LBB8_1
|
|
; CHECK-NEXT: # %bb.2: # %middle.block
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a2, a1, 4
|
|
; CHECK-NEXT: add a1, a2, a1
|
|
; CHECK-NEXT: add sp, sp, a1
|
|
; CHECK-NEXT: .cfi_def_cfa sp, 16
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%broadcast.splatinsert = insertelement <vscale x 16 x i64> zeroinitializer, i64 %0, i64 0
|
|
%broadcast.splat = shufflevector <vscale x 16 x i64> %broadcast.splatinsert, <vscale x 16 x i64> zeroinitializer, <vscale x 16 x i32> zeroinitializer
|
|
br label %vector.body
|
|
|
|
vector.body: ; preds = %vector.body, %entry
|
|
%vec.ind = phi <vscale x 16 x i64> [ zeroinitializer, %entry ], [ %vec.ind.next, %vector.body ]
|
|
%3 = and <vscale x 16 x i64> %vec.ind, %broadcast.splat
|
|
%4 = icmp ne <vscale x 16 x i64> %3, zeroinitializer
|
|
store <vscale x 16 x i64> %broadcast.splat, ptr %p
|
|
%5 = tail call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %4)
|
|
%vec.ind.next = or <vscale x 16 x i64> %vec.ind, %1
|
|
br i1 %5, label %middle.block, label %vector.body
|
|
|
|
middle.block: ; preds = %vector.body
|
|
%and.i = and i64 1, %0
|
|
ret i64 %and.i
|
|
}
|