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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

65 lines
3.2 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"
define i32 @_ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_(<vscale x 4 x i32> %wide.load, <vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %3) #0 {
; CHECK-LABEL: _ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, ma
; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: .LBB0_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: vmv2r.v v16, v10
; CHECK-NEXT: vle32.v v16, (a0), v0.t
; CHECK-NEXT: vand.vi v16, v16, 1
; CHECK-NEXT: vmsne.vi v9, v16, 0
; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: vmerge.vim v12, v12, -1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vor.vi v14, v14, 1, v0.t
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: j .LBB0_1
entry:
br label %vector.body
vector.body: ; preds = %vector.body, %entry
%index = phi i64 [ 0, %entry ], [ 1, %vector.body ]
%vec.phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %predphi88, %vector.body ]
%vec.phi81 = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %predphi93, %vector.body ]
%wide.load1 = load <vscale x 4 x i32>, ptr null, align 4
%4 = icmp slt <vscale x 4 x i32> %wide.load, zeroinitializer
%5 = icmp sgt <vscale x 4 x i32> %wide.load, zeroinitializer
%wide.masked.load82 = tail call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr null, i32 1, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> zeroinitializer)
%6 = icmp eq <vscale x 4 x i32> zeroinitializer, zeroinitializer
%7 = getelementptr i32, ptr null, i64 %index
%wide.masked.load83 = tail call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr %7, i32 1, <vscale x 4 x i1> %0, <vscale x 4 x i32> zeroinitializer)
%8 = select <vscale x 4 x i1> %0, <vscale x 4 x i1> %0, <vscale x 4 x i1> zeroinitializer
%9 = trunc <vscale x 4 x i32> %wide.masked.load83 to <vscale x 4 x i1>
%narrow = select <vscale x 4 x i1> %0, <vscale x 4 x i1> %9, <vscale x 4 x i1> zeroinitializer
%10 = sext <vscale x 4 x i1> %narrow to <vscale x 4 x i32>
%predphi88 = or <vscale x 4 x i32> %vec.phi, %10
%11 = zext <vscale x 4 x i1> %0 to <vscale x 4 x i32>
%predphi93 = or <vscale x 4 x i32> %vec.phi81, %11
%index.next = add i64 0, 1
br i1 false, label %middle.block, label %vector.body
middle.block: ; preds = %vector.body
%12 = tail call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %vec.phi)
%13 = tail call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %vec.phi81)
ret i32 %13
}
; uselistorder directives
uselistorder ptr @llvm.masked.load.nxv4i32.p0, { 1, 0 }
uselistorder ptr @llvm.vector.reduce.add.nxv4i32, { 1, 0 }
attributes #0 = { "target-features"="+v" }