derek.holloway
7502bf64a4
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137 lines
4.4 KiB
LLVM
137 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
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define void @rvv_vla(i64 %n, i64 %i) nounwind {
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; CHECK-LABEL: rvv_vla:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -32
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; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; CHECK-NEXT: addi s0, sp, 32
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: slli a2, a2, 2
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; CHECK-NEXT: sub sp, sp, a2
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; CHECK-NEXT: slli a0, a0, 2
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; CHECK-NEXT: addi a0, a0, 15
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; CHECK-NEXT: andi a0, a0, -16
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; CHECK-NEXT: sub a0, sp, a0
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; CHECK-NEXT: mv sp, a0
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: sub a2, s0, a2
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; CHECK-NEXT: addi a2, a2, -32
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; CHECK-NEXT: vl1re64.v v8, (a2)
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: slli a2, a2, 2
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; CHECK-NEXT: sub a2, s0, a2
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; CHECK-NEXT: addi a2, a2, -32
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; CHECK-NEXT: slli a1, a1, 2
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; CHECK-NEXT: vl2re64.v v8, (a2)
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; CHECK-NEXT: add a0, a0, a1
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; CHECK-NEXT: lw zero, 0(a0)
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; CHECK-NEXT: addi sp, s0, -32
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; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 32
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; CHECK-NEXT: ret
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%vla.addr = alloca i32, i64 %n
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%v1.addr = alloca <vscale x 1 x i64>
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%v1 = load volatile <vscale x 1 x i64>, ptr %v1.addr
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%v2.addr = alloca <vscale x 2 x i64>
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%v2 = load volatile <vscale x 2 x i64>, ptr %v2.addr
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%p = getelementptr i32, ptr %vla.addr, i64 %i
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%s = load volatile i32, ptr %p
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ret void
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}
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define void @rvv_overaligned() nounwind {
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; CHECK-LABEL: rvv_overaligned:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -128
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; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
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; CHECK-NEXT: addi s0, sp, 128
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 2
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; CHECK-NEXT: sub sp, sp, a0
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; CHECK-NEXT: andi sp, sp, -64
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a1, a0, 1
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; CHECK-NEXT: add a0, a1, a0
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 112
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; CHECK-NEXT: vl1re64.v v8, (a0)
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; CHECK-NEXT: addi a0, sp, 112
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; CHECK-NEXT: vl2re64.v v8, (a0)
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; CHECK-NEXT: lw zero, 64(sp)
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; CHECK-NEXT: addi sp, s0, -128
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; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 128
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; CHECK-NEXT: ret
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%overaligned = alloca i32, align 64
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%v1.addr = alloca <vscale x 1 x i64>
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%v1 = load volatile <vscale x 1 x i64>, ptr %v1.addr
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%v2.addr = alloca <vscale x 2 x i64>
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%v2 = load volatile <vscale x 2 x i64>, ptr %v2.addr
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%s = load volatile i32, ptr %overaligned, align 64
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ret void
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}
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define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
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; CHECK-LABEL: rvv_vla_and_overaligned:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -144
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; CHECK-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s1, 120(sp) # 8-byte Folded Spill
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; CHECK-NEXT: addi s0, sp, 144
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: slli a2, a2, 2
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; CHECK-NEXT: sub sp, sp, a2
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; CHECK-NEXT: andi sp, sp, -64
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; CHECK-NEXT: mv s1, sp
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; CHECK-NEXT: slli a0, a0, 2
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; CHECK-NEXT: addi a0, a0, 15
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; CHECK-NEXT: andi a0, a0, -16
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; CHECK-NEXT: sub a0, sp, a0
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; CHECK-NEXT: mv sp, a0
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: slli a3, a2, 1
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; CHECK-NEXT: add a2, a3, a2
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; CHECK-NEXT: add a2, s1, a2
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; CHECK-NEXT: addi a2, a2, 112
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; CHECK-NEXT: vl1re64.v v8, (a2)
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; CHECK-NEXT: addi a2, s1, 112
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; CHECK-NEXT: slli a1, a1, 2
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; CHECK-NEXT: vl2re64.v v8, (a2)
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; CHECK-NEXT: lw zero, 64(s1)
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; CHECK-NEXT: add a0, a0, a1
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; CHECK-NEXT: lw zero, 0(a0)
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; CHECK-NEXT: addi sp, s0, -144
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; CHECK-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s1, 120(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 144
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; CHECK-NEXT: ret
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%overaligned = alloca i32, align 64
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%vla.addr = alloca i32, i64 %n
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%v1.addr = alloca <vscale x 1 x i64>
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%v1 = load volatile <vscale x 1 x i64>, ptr %v1.addr
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%v2.addr = alloca <vscale x 2 x i64>
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%v2 = load volatile <vscale x 2 x i64>, ptr %v2.addr
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%s1 = load volatile i32, ptr %overaligned, align 64
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%p = getelementptr i32, ptr %vla.addr, i64 %i
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%s2 = load volatile i32, ptr %p
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ret void
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}
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