derek.holloway
7502bf64a4
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296 lines
7.9 KiB
LLVM
296 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple riscv64 -mattr=+m,+v < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64,RV64-VLENUNK
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; RUN: llc -mtriple riscv32 -mattr=+m,+v < %s \
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; RUN: | FileCheck %s -check-prefix=RV32
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; RUN: llc -mtriple riscv64 -mattr=+m,+v,+zvl256b < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64,RV64-VLEN256MIN
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; RUN: llc -mtriple riscv64 -mattr=+m,+v -riscv-v-vector-bits-max=256 < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64,RV64-VLEN256MAX
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; RUN: llc -mtriple riscv64 -mattr=+m,+v,+zvl256b -riscv-v-vector-bits-max=256 < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64-VLEN256EXACT
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define i64 @vscale_zero() nounwind {
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; RV64-LABEL: vscale_zero:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: li a0, 0
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_zero:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_zero:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: li a0, 0
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, 0
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ret i64 %1
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}
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define i64 @vscale_one() nounwind {
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; RV64-LABEL: vscale_one:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: srli a0, a0, 3
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_one:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: srli a0, a0, 3
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_one:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: li a0, 4
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, 1
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ret i64 %1
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}
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define i64 @vscale_uimmpow2xlen() nounwind {
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; RV64-LABEL: vscale_uimmpow2xlen:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: slli a0, a0, 3
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_uimmpow2xlen:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: slli a0, a0, 3
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_uimmpow2xlen:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: li a0, 256
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, 64
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ret i64 %1
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}
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define i64 @vscale_non_pow2() nounwind {
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; RV64-LABEL: vscale_non_pow2:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: slli a1, a0, 1
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_non_pow2:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: slli a1, a0, 1
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_non_pow2:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: li a0, 96
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, 24
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ret i64 %1
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}
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; vscale will always be a positive number, but we don't know that until after op
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; legalization. The and will be considered a NOP and replaced with its input,
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; but not until after the select becomes RISCVISD::SELECT_CC. Make sure we
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; simplify this and don't leave behind any code for calculating the select
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; condition.
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define i64 @vscale_select(i32 %x, i32 %y) {
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; RV64-LABEL: vscale_select:
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; RV64: # %bb.0:
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: srli a0, a0, 3
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_select:
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; RV32: # %bb.0:
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: srli a0, a0, 3
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_select:
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; RV64-VLEN256EXACT: # %bb.0:
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; RV64-VLEN256EXACT-NEXT: li a0, 4
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; RV64-VLEN256EXACT-NEXT: ret
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%a = call i64 @llvm.vscale.i64()
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%b = and i64 %a, 4294967295
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%c = icmp eq i32 %x, %y
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%d = select i1 %c, i64 %a, i64 %b
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ret i64 %d
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}
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define i64 @vscale_high_bits_zero() nounwind {
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; RV64-LABEL: vscale_high_bits_zero:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: srli a0, a0, 3
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_high_bits_zero:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: srli a0, a0, 3
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_high_bits_zero:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: li a0, 4
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = and i64 %0, 2047
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ret i64 %1
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}
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define i64 @vscale_masked() nounwind {
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; RV64-VLENUNK-LABEL: vscale_masked:
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; RV64-VLENUNK: # %bb.0: # %entry
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; RV64-VLENUNK-NEXT: csrr a0, vlenb
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; RV64-VLENUNK-NEXT: srli a0, a0, 3
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; RV64-VLENUNK-NEXT: andi a0, a0, 510
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; RV64-VLENUNK-NEXT: ret
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;
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; RV32-LABEL: vscale_masked:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: srli a0, a0, 3
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; RV32-NEXT: andi a0, a0, 510
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256MIN-LABEL: vscale_masked:
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; RV64-VLEN256MIN: # %bb.0: # %entry
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; RV64-VLEN256MIN-NEXT: csrr a0, vlenb
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; RV64-VLEN256MIN-NEXT: srli a0, a0, 3
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; RV64-VLEN256MIN-NEXT: andi a0, a0, 508
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; RV64-VLEN256MIN-NEXT: ret
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;
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; RV64-VLEN256MAX-LABEL: vscale_masked:
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; RV64-VLEN256MAX: # %bb.0: # %entry
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; RV64-VLEN256MAX-NEXT: csrr a0, vlenb
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; RV64-VLEN256MAX-NEXT: srli a0, a0, 3
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; RV64-VLEN256MAX-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_masked:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: li a0, 4
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = and i64 %0, 511
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ret i64 %1
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}
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define i64 @vscale_umin() vscale_range(4,1024) nounwind {
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; RV64-LABEL: vscale_umin:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: li a0, 4
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_umin:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a0, 4
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_umin:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: li a0, 4
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, 4
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%2 = call i64 @llvm.umin(i64 %1, i64 4)
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ret i64 %2
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}
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define i64 @vscale_umax() vscale_range(4,1024) nounwind {
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; RV64-LABEL: vscale_umax:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: lui a0, 1
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_umax:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: lui a0, 1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_umax:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: lui a0, 1
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, 4
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%2 = call i64 @llvm.umax(i64 %1, i64 4096)
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ret i64 %2
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}
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define i64 @vscale_smin() vscale_range(4,1024) nounwind {
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; RV64-LABEL: vscale_smin:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: li a0, 4
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_smin:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a0, 4
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_smin:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: li a0, 4
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, 4
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%2 = call i64 @llvm.smin(i64 %1, i64 4)
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ret i64 %2
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}
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define i64 @vscale_smax() vscale_range(4,1024) nounwind {
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; RV64-LABEL: vscale_smax:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: lui a0, 1
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; RV64-NEXT: ret
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;
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; RV32-LABEL: vscale_smax:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: lui a0, 1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-VLEN256EXACT-LABEL: vscale_smax:
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; RV64-VLEN256EXACT: # %bb.0: # %entry
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; RV64-VLEN256EXACT-NEXT: lui a0, 1
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; RV64-VLEN256EXACT-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, 4
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%2 = call i64 @llvm.smax(i64 %1, i64 4096)
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ret i64 %2
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}
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