derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
336 lines
12 KiB
LLVM
336 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
|
|
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64f,+zvfh,+xsfvfexpa \
|
|
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
|
|
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64f,+zvfh,+xsfvfexpa \
|
|
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
|
|
|
|
define <vscale x 1 x float> @test_intrinsic_sf_vfexpa_v_nxv1f32(<vscale x 1 x float> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv1f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32(
|
|
<vscale x 1 x float> poison,
|
|
<vscale x 1 x float> %0,
|
|
iXLen %1)
|
|
ret <vscale x 1 x float> %f
|
|
}
|
|
|
|
define <vscale x 2 x float> @test_intrinsic_sf_vfexpa_v_nxv2f32(<vscale x 2 x float> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv2f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32(
|
|
<vscale x 2 x float> poison,
|
|
<vscale x 2 x float> %0,
|
|
iXLen %1)
|
|
ret <vscale x 2 x float> %f
|
|
}
|
|
|
|
define <vscale x 4 x float> @test_intrinsic_sf_vfexpa_v_nxv4f32(<vscale x 4 x float> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv4f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32(
|
|
<vscale x 4 x float> poison,
|
|
<vscale x 4 x float> %0,
|
|
iXLen %1)
|
|
ret <vscale x 4 x float> %f
|
|
}
|
|
|
|
define <vscale x 8 x float> @test_intrinsic_sf_vfexpa_v_nxv8f32(<vscale x 8 x float> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv8f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32(
|
|
<vscale x 8 x float> poison,
|
|
<vscale x 8 x float> %0,
|
|
iXLen %1)
|
|
ret <vscale x 8 x float> %f
|
|
}
|
|
|
|
define <vscale x 16 x float> @test_intrinsic_sf_vfexpa_v_nxv16f32(<vscale x 16 x float> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv16f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32(
|
|
<vscale x 16 x float> poison,
|
|
<vscale x 16 x float> %0,
|
|
iXLen %1)
|
|
ret <vscale x 16 x float> %f
|
|
}
|
|
|
|
define <vscale x 1 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv1f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.mask.nxv1f32(
|
|
<vscale x 1 x float> %0,
|
|
<vscale x 1 x float> %1,
|
|
<vscale x 1 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 1 x float> %f
|
|
}
|
|
|
|
define <vscale x 2 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv2f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.mask.nxv2f32(
|
|
<vscale x 2 x float> %0,
|
|
<vscale x 2 x float> %1,
|
|
<vscale x 2 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 2 x float> %f
|
|
}
|
|
|
|
define <vscale x 4 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv4f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v10, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.mask.nxv4f32(
|
|
<vscale x 4 x float> %0,
|
|
<vscale x 4 x float> %1,
|
|
<vscale x 4 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 4 x float> %f
|
|
}
|
|
|
|
define <vscale x 8 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv8f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v12, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.mask.nxv8f32(
|
|
<vscale x 8 x float> %0,
|
|
<vscale x 8 x float> %1,
|
|
<vscale x 8 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 8 x float> %f
|
|
}
|
|
|
|
define <vscale x 16 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv16f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v16, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.mask.nxv16f32(
|
|
<vscale x 16 x float> %0,
|
|
<vscale x 16 x float> %1,
|
|
<vscale x 16 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 16 x float> %f
|
|
}
|
|
|
|
define <vscale x 1 x half> @test_intrinsic_sf_vfexpa_v_nxv1f16(<vscale x 1 x half> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv1f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16(
|
|
<vscale x 1 x half> poison,
|
|
<vscale x 1 x half> %0,
|
|
iXLen %1)
|
|
ret <vscale x 1 x half> %f
|
|
}
|
|
|
|
define <vscale x 2 x half> @test_intrinsic_sf_vfexpa_v_nxv2f16(<vscale x 2 x half> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv2f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16(
|
|
<vscale x 2 x half> poison,
|
|
<vscale x 2 x half> %0,
|
|
iXLen %1)
|
|
ret <vscale x 2 x half> %f
|
|
}
|
|
|
|
define <vscale x 4 x half> @test_intrinsic_sf_vfexpa_v_nxv4f16(<vscale x 4 x half> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv4f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16(
|
|
<vscale x 4 x half> poison,
|
|
<vscale x 4 x half> %0,
|
|
iXLen %1)
|
|
ret <vscale x 4 x half> %f
|
|
}
|
|
|
|
define <vscale x 8 x half> @test_intrinsic_sf_vfexpa_v_nxv8f16(<vscale x 8 x half> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv8f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16(
|
|
<vscale x 8 x half> poison,
|
|
<vscale x 8 x half> %0,
|
|
iXLen %1)
|
|
ret <vscale x 8 x half> %f
|
|
}
|
|
|
|
define <vscale x 16 x half> @test_intrinsic_sf_vfexpa_v_nxv16f16(<vscale x 16 x half> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv16f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16(
|
|
<vscale x 16 x half> poison,
|
|
<vscale x 16 x half> %0,
|
|
iXLen %1)
|
|
ret <vscale x 16 x half> %f
|
|
}
|
|
|
|
define <vscale x 32 x half> @test_intrinsic_sf_vfexpa_v_nxv32f16(<vscale x 32 x half> %0, iXLen %1) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv32f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v8
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16(
|
|
<vscale x 32 x half> poison,
|
|
<vscale x 32 x half> %0,
|
|
iXLen %1)
|
|
ret <vscale x 32 x half> %f
|
|
}
|
|
|
|
define <vscale x 1 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv1f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16(
|
|
<vscale x 1 x half> %0,
|
|
<vscale x 1 x half> %1,
|
|
<vscale x 1 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 1 x half> %f
|
|
}
|
|
|
|
define <vscale x 2 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv2f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.mask.nxv2f16(
|
|
<vscale x 2 x half> %0,
|
|
<vscale x 2 x half> %1,
|
|
<vscale x 2 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 2 x half> %f
|
|
}
|
|
|
|
define <vscale x 4 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv4f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.mask.nxv4f16(
|
|
<vscale x 4 x half> %0,
|
|
<vscale x 4 x half> %1,
|
|
<vscale x 4 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 4 x half> %f
|
|
}
|
|
|
|
define <vscale x 8 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv8f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v10, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.mask.nxv8f16(
|
|
<vscale x 8 x half> %0,
|
|
<vscale x 8 x half> %1,
|
|
<vscale x 8 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 8 x half> %f
|
|
}
|
|
|
|
define <vscale x 16 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv16f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v12, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.mask.nxv16f16(
|
|
<vscale x 16 x half> %0,
|
|
<vscale x 16 x half> %1,
|
|
<vscale x 16 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 16 x half> %f
|
|
}
|
|
|
|
define <vscale x 32 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %m, iXLen %vl) {
|
|
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv32f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
|
|
; CHECK-NEXT: sf.vfexpa.v v8, v16, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%f = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.mask.nxv32f16(
|
|
<vscale x 32 x half> %0,
|
|
<vscale x 32 x half> %1,
|
|
<vscale x 32 x i1> %m,
|
|
iXLen %vl,
|
|
iXLen 0)
|
|
ret <vscale x 32 x half> %f
|
|
}
|