TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/sf_vfexpa64e.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfvfexpa64e \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfvfexpa64e \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

define <vscale x 1 x double> @test_intrinsic_sf_vfexpa_v_nxv1f64(<vscale x 1 x double> %0, iXLen %1) {
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv1f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT:    sf.vfexpa.v v8, v8
; CHECK-NEXT:    ret
entry:
    %f = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64(
      <vscale x 1 x double> poison,
      <vscale x 1 x double> %0,
      iXLen %1)
    ret <vscale x 1 x double> %f
}

define <vscale x 2 x double> @test_intrinsic_sf_vfexpa_v_nxv2f64(<vscale x 2 x double> %0, iXLen %1) {
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv2f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT:    sf.vfexpa.v v8, v8
; CHECK-NEXT:    ret
entry:
    %f = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64(
      <vscale x 2 x double> poison,
      <vscale x 2 x double> %0,
      iXLen %1)
    ret <vscale x 2 x double> %f
}

define <vscale x 4 x double> @test_intrinsic_sf_vfexpa_v_nxv4f64(<vscale x 4 x double> %0, iXLen %1) {
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv4f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT:    sf.vfexpa.v v8, v8
; CHECK-NEXT:    ret
entry:
    %f = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64(
      <vscale x 4 x double> poison,
      <vscale x 4 x double> %0,
      iXLen %1)
    ret <vscale x 4 x double> %f
}

define <vscale x 8 x double> @test_intrinsic_sf_vfexpa_v_nxv8f64(<vscale x 8 x double> %0, iXLen %1) {
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv8f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT:    sf.vfexpa.v v8, v8
; CHECK-NEXT:    ret
entry:
    %f = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64(
      <vscale x 8 x double> poison,
      <vscale x 8 x double> %0,
      iXLen %1)
    ret <vscale x 8 x double> %f
}

define <vscale x 1 x double> @test_intrinsic_sf_vfexpa_v_mask_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %m, iXLen %vl) {
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv1f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT:    sf.vfexpa.v v8, v9, v0.t
; CHECK-NEXT:    ret
entry:
    %f = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64(
      <vscale x 1 x double> %0,
      <vscale x 1 x double> %1,
      <vscale x 1 x i1> %m,
      iXLen %vl,
      iXLen 0)
    ret <vscale x 1 x double> %f
}

define <vscale x 2 x double> @test_intrinsic_sf_vfexpa_v_mask_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %m, iXLen %vl) {
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv2f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT:    sf.vfexpa.v v8, v10, v0.t
; CHECK-NEXT:    ret
entry:
    %f = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64(
      <vscale x 2 x double> %0,
      <vscale x 2 x double> %1,
      <vscale x 2 x i1> %m,
      iXLen %vl,
      iXLen 0)
    ret <vscale x 2 x double> %f
}

define <vscale x 4 x double> @test_intrinsic_sf_vfexpa_v_mask_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %m, iXLen %vl) {
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv4f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT:    sf.vfexpa.v v8, v12, v0.t
; CHECK-NEXT:    ret
entry:
    %f = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64(
      <vscale x 4 x double> %0,
      <vscale x 4 x double> %1,
      <vscale x 4 x i1> %m,
      iXLen %vl,
      iXLen 0)
    ret <vscale x 4 x double> %f
}

define <vscale x 8 x double> @test_intrinsic_sf_vfexpa_v_mask_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %m, iXLen %vl) {
; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv8f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e64, m8, tu, mu
; CHECK-NEXT:    sf.vfexpa.v v8, v16, v0.t
; CHECK-NEXT:    ret
entry:
    %f = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64(
      <vscale x 8 x double> %0,
      <vscale x 8 x double> %1,
      <vscale x 8 x i1> %m,
      iXLen %vl,
      iXLen 0)
    ret <vscale x 8 x double> %f
}