derek.holloway
7502bf64a4
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161 lines
7.9 KiB
LLVM
161 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple riscv64 -mattr=+v -enable-subreg-liveness < %s | FileCheck %s
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define <vscale x 2 x float> @vrgather_all_undef(ptr %p) {
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; CHECK-LABEL: vrgather_all_undef:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
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; CHECK-NEXT: vrgather.vi v8, v9, 0
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> poison, i64 0, i64 0)
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ret <vscale x 2 x float> %0
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}
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define dso_local signext i32 @undef_early_clobber_chain() {
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; CHECK-LABEL: undef_early_clobber_chain:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -400
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; CHECK-NEXT: .cfi_def_cfa_offset 400
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; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
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; CHECK-NEXT: vrgather.vi v9, v8, 0
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; CHECK-NEXT: mv a0, sp
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; CHECK-NEXT: vse32.v v9, (a0)
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: addi sp, sp, 400
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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entry:
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%dst = alloca [100 x float], align 8
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call void @llvm.lifetime.start.p0(i64 400, ptr nonnull %dst) #4
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%0 = tail call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> poison, i64 0, i64 0)
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call void @llvm.riscv.vse.nxv2f32.i64(<vscale x 2 x float> %0, ptr nonnull %dst, i64 0)
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call void @llvm.lifetime.end.p0(i64 400, ptr nonnull %dst) #4
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ret i32 0
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}
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define internal void @SubRegLivenessUndefInPhi(i64 %cond) {
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; CHECK-LABEL: SubRegLivenessUndefInPhi:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: blez a0, .LBB2_2
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; CHECK-NEXT: # %bb.1: # %Cond1
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vadd.vi v12, v8, 1
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; CHECK-NEXT: vadd.vi v10, v8, 3
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; CHECK-NEXT: j .LBB2_3
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; CHECK-NEXT: .LBB2_2: # %Cond2
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v9
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a1, a0, 2
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: vadd.vi v10, v9, 1
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; CHECK-NEXT: vadd.vi v11, v9, 3
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; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
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; CHECK-NEXT: vslideup.vx v8, v9, a0
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; CHECK-NEXT: vslideup.vx v12, v10, a0
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; CHECK-NEXT: vslideup.vx v10, v11, a0
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; CHECK-NEXT: .LBB2_3: # %UseSR
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; CHECK-NEXT: vl1r.v v14, (zero)
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; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v15, v14, v8
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; CHECK-NEXT: vrgatherei16.vv v8, v14, v12
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vand.vv v8, v15, v8
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; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v9, v14, v10
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vand.vv v8, v8, v9
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; CHECK-NEXT: vs1r.v v8, (zero)
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; CHECK-NEXT: ret
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start:
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%0 = icmp sgt i64 %cond, 0
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br i1 %0, label %Cond1, label %Cond2
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Cond1: ; preds = %start
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%v15 = tail call <vscale x 1 x i16> @llvm.stepvector.nxv1i16()
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%v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
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%vs12.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 1)
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%v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
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%vs16.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 3)
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%v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
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br label %UseSR
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Cond2: ; preds = %start
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%v15.2 = tail call <vscale x 1 x i16> @llvm.stepvector.nxv1i16()
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%v17.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15.2, i64 1)
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%vs12.i.i.i.2 = add <vscale x 1 x i16> %v15.2, splat (i16 1)
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%v18.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i.2, i64 1)
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%vs16.i.i.i.2 = add <vscale x 1 x i16> %v15.2, splat (i16 3)
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%v20.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i.2, i64 1)
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br label %UseSR
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UseSR: ; preds = %Cond1, Cond2
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%v17.3 = phi <vscale x 8 x i16> [ %v17, %Cond1 ], [ %v17.2, %Cond2 ]
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%v18.3 = phi <vscale x 8 x i16> [ %v18, %Cond1 ], [ %v18.2, %Cond2 ]
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%v20.3 = phi <vscale x 8 x i16> [ %v20, %Cond1 ], [ %v20.2, %Cond2 ]
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%v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
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%v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17.3, i64 4)
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%v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18.3, i64 4)
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%v42 = and <vscale x 8 x i8> %v38, %v40
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%v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20.3, i64 4)
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%v60 = and <vscale x 8 x i8> %v42, %v46
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store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
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ret void
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}
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define internal void @SubRegLivenessUndef() {
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; CHECK-LABEL: SubRegLivenessUndef:
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; CHECK: # %bb.0: # %loopIR.preheader.i.i
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vadd.vi v10, v8, 1
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; CHECK-NEXT: vadd.vi v12, v8, 3
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; CHECK-NEXT: .LBB3_1: # %loopIR3.i.i
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vl1r.v v14, (zero)
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; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v15, v14, v8
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; CHECK-NEXT: vrgatherei16.vv v9, v14, v10
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vand.vv v9, v15, v9
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; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v11, v14, v12
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vand.vv v9, v9, v11
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; CHECK-NEXT: vs1r.v v9, (zero)
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; CHECK-NEXT: j .LBB3_1
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loopIR.preheader.i.i:
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%v15 = tail call <vscale x 1 x i16> @llvm.stepvector.nxv1i16()
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%v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
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%vs12.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 1)
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%v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
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%vs16.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 3)
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%v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
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br label %loopIR3.i.i
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loopIR3.i.i: ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
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%v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
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%v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17, i64 4)
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%v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18, i64 4)
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%v42 = and <vscale x 8 x i8> %v38, %v40
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%v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20, i64 4)
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%v60 = and <vscale x 8 x i8> %v42, %v46
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store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
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br label %loopIR3.i.i
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}
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define void @repeat_shuffle(<2 x double> %v, ptr noalias %q) {
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; CHECK-LABEL: repeat_shuffle:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vmv2r.v v10, v8
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; CHECK-NEXT: vslideup.vi v10, v8, 2
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; CHECK-NEXT: vse64.v v10, (a0)
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; CHECK-NEXT: ret
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%w = shufflevector <2 x double> %v, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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store <4 x double> %w, ptr %q
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ret void
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}
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