derek.holloway
7502bf64a4
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148 lines
5.1 KiB
LLVM
148 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s --check-prefix=RV64
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define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq0(<vscale x 1 x i16> %x) nounwind {
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; RV32-LABEL: test_urem_vec_even_divisor_eq0:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 1048571
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; RV32-NEXT: addi a0, a0, -1365
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; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; RV32-NEXT: vmul.vx v8, v8, a0
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; RV32-NEXT: lui a0, 3
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; RV32-NEXT: addi a0, a0, -1366
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; RV32-NEXT: vsll.vi v9, v8, 15
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; RV32-NEXT: vsrl.vi v8, v8, 1
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; RV32-NEXT: vor.vv v8, v8, v9
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; RV32-NEXT: vmsgtu.vx v0, v8, a0
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; RV32-NEXT: vmv.v.i v8, 0
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; RV32-NEXT: vmerge.vim v8, v8, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_vec_even_divisor_eq0:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 1048571
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; RV64-NEXT: addi a0, a0, -1365
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; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; RV64-NEXT: vmul.vx v8, v8, a0
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; RV64-NEXT: lui a0, 3
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; RV64-NEXT: addi a0, a0, -1366
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; RV64-NEXT: vsll.vi v9, v8, 15
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; RV64-NEXT: vsrl.vi v8, v8, 1
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; RV64-NEXT: vor.vv v8, v8, v9
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; RV64-NEXT: vmsgtu.vx v0, v8, a0
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: vmerge.vim v8, v8, -1, v0
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; RV64-NEXT: ret
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%urem = urem <vscale x 1 x i16> %x, splat (i16 6)
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%cmp = icmp ne <vscale x 1 x i16> %urem, splat (i16 0)
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%ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
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ret <vscale x 1 x i16> %ext
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}
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define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq0(<vscale x 1 x i16> %x) nounwind {
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; RV32-LABEL: test_urem_vec_odd_divisor_eq0:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 1048573
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; RV32-NEXT: addi a0, a0, -819
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; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; RV32-NEXT: vmul.vx v8, v8, a0
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; RV32-NEXT: lui a0, 3
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; RV32-NEXT: addi a0, a0, 819
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; RV32-NEXT: vmsgtu.vx v0, v8, a0
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; RV32-NEXT: vmv.v.i v8, 0
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; RV32-NEXT: vmerge.vim v8, v8, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_vec_odd_divisor_eq0:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 1048573
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; RV64-NEXT: addi a0, a0, -819
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; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; RV64-NEXT: vmul.vx v8, v8, a0
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; RV64-NEXT: lui a0, 3
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; RV64-NEXT: addi a0, a0, 819
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; RV64-NEXT: vmsgtu.vx v0, v8, a0
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: vmerge.vim v8, v8, -1, v0
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; RV64-NEXT: ret
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%urem = urem <vscale x 1 x i16> %x, splat (i16 5)
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%cmp = icmp ne <vscale x 1 x i16> %urem, splat (i16 0)
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%ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
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ret <vscale x 1 x i16> %ext
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}
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define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq1(<vscale x 1 x i16> %x) nounwind {
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; RV32-LABEL: test_urem_vec_even_divisor_eq1:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; RV32-NEXT: vadd.vi v8, v8, -1
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; RV32-NEXT: lui a0, 1048571
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; RV32-NEXT: addi a0, a0, -1365
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; RV32-NEXT: vmul.vx v8, v8, a0
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; RV32-NEXT: lui a0, 3
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; RV32-NEXT: addi a0, a0, -1366
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; RV32-NEXT: vsll.vi v9, v8, 15
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; RV32-NEXT: vsrl.vi v8, v8, 1
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; RV32-NEXT: vor.vv v8, v8, v9
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; RV32-NEXT: vmsgtu.vx v0, v8, a0
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; RV32-NEXT: vmv.v.i v8, 0
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; RV32-NEXT: vmerge.vim v8, v8, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_vec_even_divisor_eq1:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; RV64-NEXT: vadd.vi v8, v8, -1
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; RV64-NEXT: lui a0, 1048571
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; RV64-NEXT: addi a0, a0, -1365
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; RV64-NEXT: vmul.vx v8, v8, a0
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; RV64-NEXT: lui a0, 3
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; RV64-NEXT: addi a0, a0, -1366
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; RV64-NEXT: vsll.vi v9, v8, 15
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; RV64-NEXT: vsrl.vi v8, v8, 1
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; RV64-NEXT: vor.vv v8, v8, v9
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; RV64-NEXT: vmsgtu.vx v0, v8, a0
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: vmerge.vim v8, v8, -1, v0
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; RV64-NEXT: ret
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%urem = urem <vscale x 1 x i16> %x, splat (i16 6)
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%cmp = icmp ne <vscale x 1 x i16> %urem, splat (i16 1)
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%ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
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ret <vscale x 1 x i16> %ext
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}
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define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq1(<vscale x 1 x i16> %x) nounwind {
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; RV32-LABEL: test_urem_vec_odd_divisor_eq1:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; RV32-NEXT: vadd.vi v8, v8, -1
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; RV32-NEXT: lui a0, 1048573
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; RV32-NEXT: addi a0, a0, -819
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; RV32-NEXT: vmul.vx v8, v8, a0
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; RV32-NEXT: lui a0, 3
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; RV32-NEXT: addi a0, a0, 818
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; RV32-NEXT: vmsgtu.vx v0, v8, a0
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; RV32-NEXT: vmv.v.i v8, 0
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; RV32-NEXT: vmerge.vim v8, v8, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_vec_odd_divisor_eq1:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; RV64-NEXT: vadd.vi v8, v8, -1
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; RV64-NEXT: lui a0, 1048573
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; RV64-NEXT: addi a0, a0, -819
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; RV64-NEXT: vmul.vx v8, v8, a0
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; RV64-NEXT: lui a0, 3
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; RV64-NEXT: addi a0, a0, 818
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; RV64-NEXT: vmsgtu.vx v0, v8, a0
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: vmerge.vim v8, v8, -1, v0
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; RV64-NEXT: ret
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%urem = urem <vscale x 1 x i16> %x, splat (i16 5)
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%cmp = icmp ne <vscale x 1 x i16> %urem, splat (i16 1)
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%ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
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ret <vscale x 1 x i16> %ext
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}
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