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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/vabs.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

537 lines
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvabd \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvabd \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 1 x i8> @vabs_v_i8mf8(<vscale x 1 x i8> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i8mf8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.riscv.vabs(<vscale x 1 x i8> poison, <vscale x 1 x i8> %v, iXLen %vl)
ret <vscale x 1 x i8> %res
}
define <vscale x 1 x i8> @vabs_v_mask_i8mf8(<vscale x 1 x i8> %passthru, <vscale x 1 x i8> %v, <vscale x 1 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i8mf8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.riscv.vabs.mask(
<vscale x 1 x i8> %passthru,
<vscale x 1 x i8> %v,
<vscale x 1 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 1 x i8> %res
}
define <vscale x 2 x i8> @vabs_v_i8mf4(<vscale x 2 x i8> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i8mf4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.riscv.vabs(<vscale x 2 x i8> poison, <vscale x 2 x i8> %v, iXLen %vl)
ret <vscale x 2 x i8> %res
}
define <vscale x 2 x i8> @vabs_v_mask_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 2 x i8> %v, <vscale x 2 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i8mf4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.riscv.vabs.mask(
<vscale x 2 x i8> %passthru,
<vscale x 2 x i8> %v,
<vscale x 2 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 2 x i8> %res
}
define <vscale x 4 x i8> @vabs_v_i8mf2(<vscale x 4 x i8> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i8mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.riscv.vabs(<vscale x 4 x i8> poison, <vscale x 4 x i8> %v, iXLen %vl)
ret <vscale x 4 x i8> %res
}
define <vscale x 4 x i8> @vabs_v_mask_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 4 x i8> %v, <vscale x 4 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i8mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.riscv.vabs.mask(
<vscale x 4 x i8> %passthru,
<vscale x 4 x i8> %v,
<vscale x 4 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 4 x i8> %res
}
define <vscale x 8 x i8> @vabs_v_i8m1(<vscale x 8 x i8> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i8m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.riscv.vabs(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v, iXLen %vl)
ret <vscale x 8 x i8> %res
}
define <vscale x 8 x i8> @vabs_v_mask_i8m1(<vscale x 8 x i8> %passthru, <vscale x 8 x i8> %v, <vscale x 8 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i8m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.riscv.vabs.mask(
<vscale x 8 x i8> %passthru,
<vscale x 8 x i8> %v,
<vscale x 8 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 8 x i8> %res
}
define <vscale x 16 x i8> @vabs_v_i8m2(<vscale x 16 x i8> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i8m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.riscv.vabs(<vscale x 16 x i8> poison, <vscale x 16 x i8> %v, iXLen %vl)
ret <vscale x 16 x i8> %res
}
define <vscale x 16 x i8> @vabs_v_mask_i8m2(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %v, <vscale x 16 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i8m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vabs.v v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.riscv.vabs.mask(
<vscale x 16 x i8> %passthru,
<vscale x 16 x i8> %v,
<vscale x 16 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 16 x i8> %res
}
define <vscale x 32 x i8> @vabs_v_i8m4(<vscale x 32 x i8> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i8m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.riscv.vabs(<vscale x 32 x i8> poison, <vscale x 32 x i8> %v, iXLen %vl)
ret <vscale x 32 x i8> %res
}
define <vscale x 32 x i8> @vabs_v_mask_i8m4(<vscale x 32 x i8> %passthru, <vscale x 32 x i8> %v, <vscale x 32 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i8m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vabs.v v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.riscv.vabs.mask(
<vscale x 32 x i8> %passthru,
<vscale x 32 x i8> %v,
<vscale x 32 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 32 x i8> %res
}
define <vscale x 64 x i8> @vabs_v_i8m8(<vscale x 64 x i8> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i8m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.riscv.vabs(<vscale x 64 x i8> poison, <vscale x 64 x i8> %v, iXLen %vl)
ret <vscale x 64 x i8> %res
}
define <vscale x 64 x i8> @vabs_v_mask_i8m8(<vscale x 64 x i8> %passthru, <vscale x 64 x i8> %v, <vscale x 64 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i8m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vabs.v v8, v16, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.riscv.vabs.mask(
<vscale x 64 x i8> %passthru,
<vscale x 64 x i8> %v,
<vscale x 64 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 64 x i8> %res
}
define <vscale x 1 x i16> @vabs_v_i16mf4(<vscale x 1 x i16> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i16mf4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.riscv.vabs(<vscale x 1 x i16> poison, <vscale x 1 x i16> %v, iXLen %vl)
ret <vscale x 1 x i16> %res
}
define <vscale x 1 x i16> @vabs_v_mask_i16mf4(<vscale x 1 x i16> %passthru, <vscale x 1 x i16> %v, <vscale x 1 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i16mf4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.riscv.vabs.mask(
<vscale x 1 x i16> %passthru,
<vscale x 1 x i16> %v,
<vscale x 1 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 1 x i16> %res
}
define <vscale x 2 x i16> @vabs_v_i16mf2(<vscale x 2 x i16> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i16mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.riscv.vabs(<vscale x 2 x i16> poison, <vscale x 2 x i16> %v, iXLen %vl)
ret <vscale x 2 x i16> %res
}
define <vscale x 2 x i16> @vabs_v_mask_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 2 x i16> %v, <vscale x 2 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i16mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.riscv.vabs.mask(
<vscale x 2 x i16> %passthru,
<vscale x 2 x i16> %v,
<vscale x 2 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 2 x i16> %res
}
define <vscale x 4 x i16> @vabs_v_i16m1(<vscale x 4 x i16> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i16m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.riscv.vabs(<vscale x 4 x i16> poison, <vscale x 4 x i16> %v, iXLen %vl)
ret <vscale x 4 x i16> %res
}
define <vscale x 4 x i16> @vabs_v_mask_i16m1(<vscale x 4 x i16> %passthru, <vscale x 4 x i16> %v, <vscale x 4 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i16m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.riscv.vabs.mask(
<vscale x 4 x i16> %passthru,
<vscale x 4 x i16> %v,
<vscale x 4 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 4 x i16> %res
}
define <vscale x 8 x i16> @vabs_v_i16m2(<vscale x 8 x i16> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i16m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.riscv.vabs(<vscale x 8 x i16> poison, <vscale x 8 x i16> %v, iXLen %vl)
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @vabs_v_mask_i16m2(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %v, <vscale x 8 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i16m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vabs.v v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.riscv.vabs.mask(
<vscale x 8 x i16> %passthru,
<vscale x 8 x i16> %v,
<vscale x 8 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 8 x i16> %res
}
define <vscale x 16 x i16> @vabs_v_i16m4(<vscale x 16 x i16> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i16m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.riscv.vabs(<vscale x 16 x i16> poison, <vscale x 16 x i16> %v, iXLen %vl)
ret <vscale x 16 x i16> %res
}
define <vscale x 16 x i16> @vabs_v_mask_i16m4(<vscale x 16 x i16> %passthru, <vscale x 16 x i16> %v, <vscale x 16 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i16m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vabs.v v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.riscv.vabs.mask(
<vscale x 16 x i16> %passthru,
<vscale x 16 x i16> %v,
<vscale x 16 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 16 x i16> %res
}
define <vscale x 32 x i16> @vabs_v_i16m8(<vscale x 32 x i16> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i16m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.riscv.vabs(<vscale x 32 x i16> poison, <vscale x 32 x i16> %v, iXLen %vl)
ret <vscale x 32 x i16> %res
}
define <vscale x 32 x i16> @vabs_v_mask_i16m8(<vscale x 32 x i16> %passthru, <vscale x 32 x i16> %v, <vscale x 32 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i16m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vabs.v v8, v16, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.riscv.vabs.mask(
<vscale x 32 x i16> %passthru,
<vscale x 32 x i16> %v,
<vscale x 32 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 32 x i16> %res
}
define <vscale x 1 x i32> @vabs_v_i32mf2(<vscale x 1 x i32> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i32mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.riscv.vabs(<vscale x 1 x i32> poison, <vscale x 1 x i32> %v, iXLen %vl)
ret <vscale x 1 x i32> %res
}
define <vscale x 1 x i32> @vabs_v_mask_i32mf2(<vscale x 1 x i32> %passthru, <vscale x 1 x i32> %v, <vscale x 1 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i32mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.riscv.vabs.mask(
<vscale x 1 x i32> %passthru,
<vscale x 1 x i32> %v,
<vscale x 1 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 1 x i32> %res
}
define <vscale x 2 x i32> @vabs_v_i32m1(<vscale x 2 x i32> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i32m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.riscv.vabs(<vscale x 2 x i32> poison, <vscale x 2 x i32> %v, iXLen %vl)
ret <vscale x 2 x i32> %res
}
define <vscale x 2 x i32> @vabs_v_mask_i32m1(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %v, <vscale x 2 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i32m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.riscv.vabs.mask(
<vscale x 2 x i32> %passthru,
<vscale x 2 x i32> %v,
<vscale x 2 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 2 x i32> %res
}
define <vscale x 4 x i32> @vabs_v_i32m2(<vscale x 4 x i32> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i32m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.riscv.vabs(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, iXLen %vl)
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @vabs_v_mask_i32m2(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %v, <vscale x 4 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i32m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vabs.v v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.riscv.vabs.mask(
<vscale x 4 x i32> %passthru,
<vscale x 4 x i32> %v,
<vscale x 4 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 4 x i32> %res
}
define <vscale x 8 x i32> @vabs_v_i32m4(<vscale x 8 x i32> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i32m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.riscv.vabs(<vscale x 8 x i32> poison, <vscale x 8 x i32> %v, iXLen %vl)
ret <vscale x 8 x i32> %res
}
define <vscale x 8 x i32> @vabs_v_mask_i32m4(<vscale x 8 x i32> %passthru, <vscale x 8 x i32> %v, <vscale x 8 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i32m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vabs.v v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.riscv.vabs.mask(
<vscale x 8 x i32> %passthru,
<vscale x 8 x i32> %v,
<vscale x 8 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 8 x i32> %res
}
define <vscale x 16 x i32> @vabs_v_i32m8(<vscale x 16 x i32> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i32m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.riscv.vabs(<vscale x 16 x i32> poison, <vscale x 16 x i32> %v, iXLen %vl)
ret <vscale x 16 x i32> %res
}
define <vscale x 16 x i32> @vabs_v_mask_i32m8(<vscale x 16 x i32> %passthru, <vscale x 16 x i32> %v, <vscale x 16 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i32m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vabs.v v8, v16, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.riscv.vabs.mask(
<vscale x 16 x i32> %passthru,
<vscale x 16 x i32> %v,
<vscale x 16 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 16 x i32> %res
}
define <vscale x 1 x i64> @vabs_v_i64m1(<vscale x 1 x i64> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i64m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.riscv.vabs(<vscale x 1 x i64> poison, <vscale x 1 x i64> %v, iXLen %vl)
ret <vscale x 1 x i64> %res
}
define <vscale x 1 x i64> @vabs_v_mask_i64m1(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %v, <vscale x 1 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i64m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vabs.v v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.riscv.vabs.mask(
<vscale x 1 x i64> %passthru,
<vscale x 1 x i64> %v,
<vscale x 1 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 1 x i64> %res
}
define <vscale x 2 x i64> @vabs_v_i64m2(<vscale x 2 x i64> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i64m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.riscv.vabs(<vscale x 2 x i64> poison, <vscale x 2 x i64> %v, iXLen %vl)
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @vabs_v_mask_i64m2(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %v, <vscale x 2 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i64m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vabs.v v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.riscv.vabs.mask(
<vscale x 2 x i64> %passthru,
<vscale x 2 x i64> %v,
<vscale x 2 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 2 x i64> %res
}
define <vscale x 4 x i64> @vabs_v_i64m4(<vscale x 4 x i64> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i64m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.riscv.vabs(<vscale x 4 x i64> poison, <vscale x 4 x i64> %v, iXLen %vl)
ret <vscale x 4 x i64> %res
}
define <vscale x 4 x i64> @vabs_v_mask_i64m4(<vscale x 4 x i64> %passthru, <vscale x 4 x i64> %v, <vscale x 4 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i64m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vabs.v v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.riscv.vabs.mask(
<vscale x 4 x i64> %passthru,
<vscale x 4 x i64> %v,
<vscale x 4 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 4 x i64> %res
}
define <vscale x 8 x i64> @vabs_v_i64m8(<vscale x 8 x i64> %v, iXLen %vl) {
; CHECK-LABEL: vabs_v_i64m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vabs.v v8, v8
; CHECK-NEXT: ret
%res = call <vscale x 8 x i64> @llvm.riscv.vabs(<vscale x 8 x i64> poison, <vscale x 8 x i64> %v, iXLen %vl)
ret <vscale x 8 x i64> %res
}
define <vscale x 8 x i64> @vabs_v_mask_i64m8(<vscale x 8 x i64> %passthru, <vscale x 8 x i64> %v, <vscale x 8 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabs_v_mask_i64m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vabs.v v8, v16, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i64> @llvm.riscv.vabs.mask(
<vscale x 8 x i64> %passthru,
<vscale x 8 x i64> %v,
<vscale x 8 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 8 x i64> %res
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
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