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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/vfmsac-bf.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

424 lines
16 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
define <vscale x 1 x bfloat> @intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, ma
; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16(
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %1,
<vscale x 1 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfmsac_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.mask.nxv1bf16.nxv1bf16(
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %1,
<vscale x 1 x bfloat> %2,
<vscale x 1 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vfmsac_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2bf16_nxv2bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, ma
; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16(
<vscale x 2 x bfloat> %0,
<vscale x 2 x bfloat> %1,
<vscale x 2 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vfmsac_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.mask.nxv2bf16.nxv2bf16(
<vscale x 2 x bfloat> %0,
<vscale x 2 x bfloat> %1,
<vscale x 2 x bfloat> %2,
<vscale x 2 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vfmsac_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4bf16_nxv4bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, ma
; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16(
<vscale x 4 x bfloat> %0,
<vscale x 4 x bfloat> %1,
<vscale x 4 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vfmsac_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.mask.nxv4bf16.nxv4bf16(
<vscale x 4 x bfloat> %0,
<vscale x 4 x bfloat> %1,
<vscale x 4 x bfloat> %2,
<vscale x 4 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vfmsac_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8bf16_nxv8bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, ma
; CHECK-NEXT: vfmsac.vv v8, v10, v12
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16(
<vscale x 8 x bfloat> %0,
<vscale x 8 x bfloat> %1,
<vscale x 8 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vfmsac_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.mask.nxv8bf16.nxv8bf16(
<vscale x 8 x bfloat> %0,
<vscale x 8 x bfloat> %1,
<vscale x 8 x bfloat> %2,
<vscale x 8 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vfmsac_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16bf16_nxv16bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, ma
; CHECK-NEXT: vfmsac.vv v8, v12, v16
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfmsac.nxv16bf16.nxv16bf16(
<vscale x 16 x bfloat> %0,
<vscale x 16 x bfloat> %1,
<vscale x 16 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vfmsac_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfmsac.mask.nxv16bf16.nxv16bf16(
<vscale x 16 x bfloat> %0,
<vscale x 16 x bfloat> %1,
<vscale x 16 x bfloat> %2,
<vscale x 16 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfmsac_vf_nxv1bf16_bf16_nxv1bf16(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1bf16_bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, ma
; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16(
<vscale x 1 x bfloat> %0,
bfloat %1,
<vscale x 1 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfmsac_mask_vf_nxv1bf16_bf16_nxv1bf16(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1bf16_bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.mask.nxv1bf16.bf16(
<vscale x 1 x bfloat> %0,
bfloat %1,
<vscale x 1 x bfloat> %2,
<vscale x 1 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vfmsac_vf_nxv2bf16_bf16_nxv2bf16(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2bf16_bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, ma
; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16(
<vscale x 2 x bfloat> %0,
bfloat %1,
<vscale x 2 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vfmsac_mask_vf_nxv2bf16_bf16_nxv2bf16(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2bf16_bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.mask.nxv2bf16.bf16(
<vscale x 2 x bfloat> %0,
bfloat %1,
<vscale x 2 x bfloat> %2,
<vscale x 2 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vfmsac_vf_nxv4bf16_bf16_nxv4bf16(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4bf16_bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, ma
; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16(
<vscale x 4 x bfloat> %0,
bfloat %1,
<vscale x 4 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vfmsac_mask_vf_nxv4bf16_bf16_nxv4bf16(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4bf16_bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.mask.nxv4bf16.bf16(
<vscale x 4 x bfloat> %0,
bfloat %1,
<vscale x 4 x bfloat> %2,
<vscale x 4 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vfmsac_vf_nxv8bf16_bf16_nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8bf16_bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, ma
; CHECK-NEXT: vfmsac.vf v8, fa0, v10
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16(
<vscale x 8 x bfloat> %0,
bfloat %1,
<vscale x 8 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vfmsac_mask_vf_nxv8bf16_bf16_nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8bf16_bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.mask.nxv8bf16.bf16(
<vscale x 8 x bfloat> %0,
bfloat %1,
<vscale x 8 x bfloat> %2,
<vscale x 8 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vfmsac_vf_nxv16bf16_bf16_nxv16bf16(<vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16bf16_bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, ma
; CHECK-NEXT: vfmsac.vf v8, fa0, v12
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfmsac.nxv16bf16.bf16(
<vscale x 16 x bfloat> %0,
bfloat %1,
<vscale x 16 x bfloat> %2,
iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vfmsac_mask_vf_nxv16bf16_bf16_nxv16bf16(<vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16bf16_bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfmsac.mask.nxv16bf16.bf16(
<vscale x 16 x bfloat> %0,
bfloat %1,
<vscale x 16 x bfloat> %2,
<vscale x 16 x i1> %3,
iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16_commute(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16_commute:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT: vfmsub.vv v8, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16(
<vscale x 1 x bfloat> %1,
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %2,
iXLen 7, iXLen %3, iXLen 3)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16_commute2(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16_commute2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT: vfmsub.vv v8, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16(
<vscale x 1 x bfloat> %1,
<vscale x 1 x bfloat> %2,
<vscale x 1 x bfloat> %0,
iXLen 7, iXLen %3, iXLen 3)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfmsac_vf_nxv1bf16_bf16_nxv1bf16_commute(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1bf16_bf16_nxv1bf16_commute:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT: vfmsub.vf v8, fa0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16(
<vscale x 1 x bfloat> %2,
bfloat %1,
<vscale x 1 x bfloat> %0,
iXLen 7, iXLen %3, iXLen 3)
ret <vscale x 1 x bfloat> %a
}
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